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Erschienen in:
2013 | OriginalPaper | Buchkapitel
OMHI 2012: First International Workshop on On-chip Memory Hierarchies and Interconnects: Organization, Management and Implementation
verfasst von : Julio Sahuquillo, María E. Gómez, Salvador Petit
Erschienen in: Euro-Par 2012: Parallel Processing Workshops
Verlag: Springer Berlin Heidelberg
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Current CMPs include high amounts of on-chip memory storage, organized either as caches or main memory to avoid the huge latencies of accessing offchip DRAM memory. To address internal data access latencies, a fast on-chip network interconnects the memory hierarchy within the processor chip. As a consequence, performance, area, and power consumption of current chip multiprocessors (CMPs) are highly dominated by the on-chip memory hierarchy and interconnect design. This problem aggravates with the increasing number of cores since a wider and likely deeper on-chip memory hierarchy is required.