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Erschienen in:
General Issues of Gate-Level Simulation and Optimization of Digital Circuits with Consideration of Destabilizing Factors Kapitel lesen Erstes Kapitel lesen

2018 | OriginalPaper | Buchkapitel

5. Optimization of Digital Circuits with Consideration of DF

verfasst von : Vazgen Melikyan

Erschienen in: Simulation and Optimization of Digital Circuits

Verlag: Springer International Publishing

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Abstract

An algorithm for optimizing the critical timing paths of digital circuits, taking into account the influence of destabilizing factors with the minimal growth of power consumption by the circuit is described. The algorithm is tested on digital circuits of the ISCAS89 series. An algorithm to solve the problem of reducing the level of power consumption of digital circuits, taking into account the influence of destabilizing factors at the expense of the use of the speed margin in the design options of digital circuits is also described.

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Vorheriges Kapitel Algorithmic Implementation of the Automated System of Gate-Level Simulation of Digital Circuits with Consideration of DF
Nächstes Kapitel Linguistic and Software Development of the Automated System of Gate-Level Simulation of Digital Circuits with Consideration of DF
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Metadaten
Titel
Optimization of Digital Circuits with Consideration of DF
verfasst von
Vazgen Melikyan
Copyright-Jahr
2018
Buch
Simulation and Optimization of Digital Circuits

Print ISBN: 978-3-319-71636-7

Electronic ISBN: 978-3-319-71637-4

Copyright-Jahr: 2018

DOI
https://doi.org/10.1007/978-3-319-71637-4_5

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