Parallel Architectures

For all its virtues, the stored-program computer paradigm contains a significant defect – the “von Neumann bottleneck.” The bottleneck is caused by the fact that both data and instruction access uses the same bus, which has limited bandwidth. The processor, therefore, has to balance the number of instructions executed against the amount of data to be accessed. Furthermore, the stored program concept is inherently sequential, which does not work easily with the various parallel models of computation. High-speed memory internal and external to the processor, mitigates the problem, but also creates a cache coherence problem necessitating that the cache be kept in sync with main memory.