Parasitic Substrate Coupling in High Voltage Integrated Circuits

Minority and Majority Carriers Propagation in Semiconductor Substrate

verfasst von: Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese

Verlag: Springer International Publishing

Buchreihe : Analog Circuits and Signal Processing

Enthalten in: Springer Professional "Wirtschaft+Technik" , Springer Professional "Technik"

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Über dieses Buch

This book introduces a new approach to model and predict substrate parasitic failures in integrated circuits with standard circuit design tools.

The injection of majority and minority carriers in the substrate is a recurring problem in smart power ICs containing high voltage, high current switching devices besides sensitive control, protection and signal processing circuits.

The injection of parasitic charges leads to the activation of substrate bipolar transistors. This book explores how these events can be evaluated for a wide range of circuit topologies. To this purpose, new generalized devices implemented in Verilog-A are used to model the substrate with standard circuit simulators. This approach was able to predict for the first time the activation of a latch-up in real circuits through post-layout SPICE simulation analysis.

Discusses substrate modeling and circuit-level simulation of parasitic bipolar device coupling effects in integrated circuits;

Includes circuit back-annotation of the parasitic lateral n-p-n and vertical p-n-p bipolar transistors in the substrate;

Uses Spice for simulation and characterization of parasitic bipolar transistors, latch-up of the parasitic p-n-p-n structure, and electrostatic discharge (ESD) protection devices;

Offers design guidelines to reduce couplings by adding specific protections.

Inhaltsverzeichnis

Frontmatter

Chapter 1. Overview of Parasitic Substrate Coupling

Abstract

Major issues related to the parasitic substrate current in integrated circuits and related engineering solutions are introduced in this chapter. The main cause for electrical couplings taking place in the substrate has been attributed to the activation of parasitic transistors. These devices can be identified from the layout, but still the analysis of parasitic substrate current cannot be restricted to the analysis of parasitic transistors only. In essence, a predictive analysis of substrate coupling mechanisms requires that minority and majority carriers are taken into account in circuit simulators. One could argue that minority carriers are already included in compact models. For instance, the model for the bipolar transistor does include the minority carriers. But these minority carriers are never “propagated” between the different devices, and, for instance, simulating a np-pn connection of diodes does not predict the characteristics of a BJT. An overview of the strategies proposed so far to simulate parasitic signals in IC substrates is presented in the state-of-the-art section. In general, circuit designers use specific tools to fix severe substrate coupling mechanisms, and, to avoid failures and costly redesign processes, this analysis is done during the design phase of the circuit.