Performance Analysis for Tri-Gate Junction-Less FET by Employing Trioxide and Rectangular Core Shell (RCS) Architecture

With the advancement in technology scaling and featuring new device design is being explored to meet the demand for low power and high-speed circuit design. Tri-gate junction-less FET (TGJLFET) is taken as a reference model in this study. The structure of the reference model is modified to arrive at three different device structures; the first one with two dielectric materials for gate oxide, the second one with three dielectric materials, and the third with three dielectric materials with Rectangular Core–shell (RCS) Architecture having opposite doping at the center of the channel. The performance of these three new structures was evaluated and compared with one another and also with the reference model structure. Investigated performance parameters include leakage current, sub-threshold swing, Drain induced barrier lowering (DIBL), threshold voltage, transconductance (Gm), Output Conductance (Gd), Early Voltage (Ve), Intrinsic Gain (Av), the potential at core and surface fin of the Tri-gate device. The simulation results reveal that the device with gate trioxide with RCS Architecture shows good performance with respect to the above parameters when compared with the two new device structures and reference model. Further, an inverter is simulated using TGJLFET trioxide with RCS Architecture and its DC analysis and signal to noise margin were studied. For all the simulations 3D visual TCAD device simulator from Cogenda Pvt Ltd is used.