In  Raddum and Semaev propose a technique to solve systems of polynomial equations over
as occurring in algebraic attacks on block ciphers. This approach is known as
, and we present a special purpose architecture to implement MRHS in a dedicated hardware device. Our preliminary performance analysis of this
limination shows that the use of ASICs seems to enable significant performance gains over a software implementation of MRHS. The main parts of the proposed architecture are scalable, the limiting factor being mainly the available bandwidth for interchip communication. Our focus is on a design choice that can be implemented within the limits of available fab technology. The proposed design can be expected to offer a running time improvement in the order of several magnitudes over a software implementation.
We do not make any claims about the practical feasibility of an attack against AES-128 with our design, as we do not see the necessary theoretical tools to be available: deriving reliable running time estimates for an algebraic attack with MRHS when being applied to a full-round version of AES-128 is still an open problem.