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2010 | OriginalPaper | Buchkapitel

2. Pipelined ADC Digital Calibration Techniques and Tradeoffs

verfasst von : Imran Ahmed

Erschienen in: Analog Circuit Design

Verlag: Springer Netherlands

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Abstract

In this paper an overview of state of the art techniques to measure and correct non-idealities in a pipelined ADC is given. The paper discusses the motivations for digital calibration, and subsequently details state of the art calibration approaches. System tradeoffs of commonly used calibration techniques are analyzed. A discussion of how digital calibration can be used to enable the next generation of very low power ‘smart-ADCs’ is also given.

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Literatur
1.
Zurück zum Zitat K. Bult, G.J.G.M. Geelen, “A fast settling CMOS op amp for SC circuits with 90-dB DB Gain”, IEEE Journal of Solid-State Circuits, vol.25, pp.1379–1384, Dec. 1990.CrossRef K. Bult, G.J.G.M. Geelen, “A fast settling CMOS op amp for SC circuits with 90-dB DB Gain”, IEEE Journal of Solid-State Circuits, vol.25, pp.1379–1384, Dec. 1990.CrossRef
2.
Zurück zum Zitat F. You, S.H.K. Embabi, E. Sanchez-Sinencio, “Multistage amplifier topologies with nested Gm-C compensation,” IEEE Journal of Solid-State Circuits, vol.32, no.12, pp.2000–2011, Dec. 1997.CrossRef F. You, S.H.K. Embabi, E. Sanchez-Sinencio, “Multistage amplifier topologies with nested Gm-C compensation,” IEEE Journal of Solid-State Circuits, vol.32, no.12, pp.2000–2011, Dec. 1997.CrossRef
3.
Zurück zum Zitat S.-H. Lee, B.-S. Song, “Simplified digital calibration for multi-stage analog-to-digital converters,” 1993 IEEE International Symposium on Circuits and Systems, 1993, ISCAS ‘93, vol.2, 3–6, pp.1216–1219, May 1993.CrossRef S.-H. Lee, B.-S. Song, “Simplified digital calibration for multi-stage analog-to-digital converters,” 1993 IEEE International Symposium on Circuits and Systems, 1993, ISCAS ‘93, vol.2, 3–6, pp.1216–1219, May 1993.CrossRef
4.
Zurück zum Zitat D.Y. Chang, J. Li, U.K. Moon, “Radix-based digitial calibration techniques for multi-stage recycling pipelined ADCs”, IEEE Transactions on Circuits and Systems I, vol.51, pp.2133–2140, Nov. 2004.CrossRef D.Y. Chang, J. Li, U.K. Moon, “Radix-based digitial calibration techniques for multi-stage recycling pipelined ADCs”, IEEE Transactions on Circuits and Systems I, vol.51, pp.2133–2140, Nov. 2004.CrossRef
5.
Zurück zum Zitat C.R. Grace, P.J. Hurst, S.H. Lewis, “A 12b 80 MS/s pipelined ADC with bootstrapped digital calibration”, in IEEE International Solid-State Circuits Conference. (ISSCC) Digital Technical Papers, pp.460–539, Feb. 2004. C.R. Grace, P.J. Hurst, S.H. Lewis, “A 12b 80 MS/s pipelined ADC with bootstrapped digital calibration”, in IEEE International Solid-State Circuits Conference. (ISSCC) Digital Technical Papers, pp.460–539, Feb. 2004.
6.
Zurück zum Zitat U.K. Moon, B.-S. Song, “Background digital calibration techniques for pipelined ADC’s”, IEEE Transactions on Circuits and Systems II, vol.44, pp.102–109, Feb. 1997.CrossRef U.K. Moon, B.-S. Song, “Background digital calibration techniques for pipelined ADC’s”, IEEE Transactions on Circuits and Systems II, vol.44, pp.102–109, Feb. 1997.CrossRef
7.
Zurück zum Zitat S.-U. Kwak, B.-S. Song, K. Bacrania, “A 15-b, 5-Msample/s low-spurious CMOS ADC,” IEEE Journal of Solid-State Circuits, vol.32, no.12, pp.1866–1875, Dec. 1997.CrossRef S.-U. Kwak, B.-S. Song, K. Bacrania, “A 15-b, 5-Msample/s low-spurious CMOS ADC,” IEEE Journal of Solid-State Circuits, vol.32, no.12, pp.1866–1875, Dec. 1997.CrossRef
8.
Zurück zum Zitat O.E. Erdogan, P.J. Hurst, S.H. Lewis, “A 12-b digital-background-calibrated algorithmic ADC with -90-dB THD,” IEEE Journal of Solid-State Circuits, vol.34, no.12, pp.1812–1820, Dec. 1999.CrossRef O.E. Erdogan, P.J. Hurst, S.H. Lewis, “A 12-b digital-background-calibrated algorithmic ADC with -90-dB THD,” IEEE Journal of Solid-State Circuits, vol.34, no.12, pp.1812–1820, Dec. 1999.CrossRef
9.
Zurück zum Zitat I. Galton, “Digital cancellation of D/A converter noise in pipelined A/D converters,” IEEE TCAS-II. vol.47, pp.185–196, Mar. 2000. I. Galton, “Digital cancellation of D/A converter noise in pipelined A/D converters,” IEEE TCAS-II. vol.47, pp.185–196, Mar. 2000.
10.
Zurück zum Zitat J. Li, U.K. Moon, “Background calibration techniques for multistage pipelined ADCs with digital redundancy,” IEEE Transactions on Circuits and Systems II, vol.50, pp.531–538, Sep. 2003.CrossRef J. Li, U.K. Moon, “Background calibration techniques for multistage pipelined ADCs with digital redundancy,” IEEE Transactions on Circuits and Systems II, vol.50, pp.531–538, Sep. 2003.CrossRef
11.
Zurück zum Zitat Y. Chiu, C.W. Tsang, B. Nikolic, P.R. Gray, “Least mean square adaptive digital background calibration of pipelined analog-to-digital converters”, IEEE TCAS-I, vol.51, pp.38–46, Jan. 2004.CrossRef Y. Chiu, C.W. Tsang, B. Nikolic, P.R. Gray, “Least mean square adaptive digital background calibration of pipelined analog-to-digital converters”, IEEE TCAS-I, vol.51, pp.38–46, Jan. 2004.CrossRef
12.
Zurück zum Zitat X. Wang, P.J. Hurst, S.H. Lewis, “A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration,” IEEE Journal of Solid-State Circuits, vol.39, no.11, pp.1799–1808, Nov. 2004.CrossRef X. Wang, P.J. Hurst, S.H. Lewis, “A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration,” IEEE Journal of Solid-State Circuits, vol.39, no.11, pp.1799–1808, Nov. 2004.CrossRef
13.
Zurück zum Zitat E. Siragusa, I. Galton, “A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC,” IEEE Journal of Solid-State Circuits, vol.39, no.12, pp. 2126–2138, Dec. 2004.CrossRef E. Siragusa, I. Galton, “A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC,” IEEE Journal of Solid-State Circuits, vol.39, no.12, pp. 2126–2138, Dec. 2004.CrossRef
14.
Zurück zum Zitat J. Li, G.-C. Ahn, D.-Y. Chang, U.-K. Moon, “A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR,” IEEE Journal of Solid-State Circuits, vol.40, no.4, pp.960–969, Apr. 2005.CrossRef J. Li, G.-C. Ahn, D.-Y. Chang, U.-K. Moon, “A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR,” IEEE Journal of Solid-State Circuits, vol.40, no.4, pp.960–969, Apr. 2005.CrossRef
15.
Zurück zum Zitat H.-C. Liu, Z.-M. Lee, J.-T. Wu, “A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration,” IEEE Journal of Solid-State Circuits, vol.40, no.5, pp.1047–1056, May 2005. H.-C. Liu, Z.-M. Lee, J.-T. Wu, “A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration,” IEEE Journal of Solid-State Circuits, vol.40, no.5, pp.1047–1056, May 2005.
16.
Zurück zum Zitat S. Ray, B.-S. Song, “A 13-b linear, 40-MS/s pipelined ADC with self-configured capacitor matching”, IEEE JSSC, vol.42, pp.463–474, Mar. 2007. S. Ray, B.-S. Song, “A 13-b linear, 40-MS/s pipelined ADC with self-configured capacitor matching”, IEEE JSSC, vol.42, pp.463–474, Mar. 2007.
17.
Zurück zum Zitat E. Siragusa, I. Galton, “A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC,” IEEE Journal of Solid-State Circuits, vol.39, no.12, pp.2126–2138, Dec. 2004.CrossRef E. Siragusa, I. Galton, “A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC,” IEEE Journal of Solid-State Circuits, vol.39, no.12, pp.2126–2138, Dec. 2004.CrossRef
18.
Zurück zum Zitat J. McNeill, M. Coln, B. Larivee, “A split-ADC architecture for deterministic digital background calibration of a 16b 1 MS/s ADC,” Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International, vol.48, 6–10, pp.276–598, Feb. 2005.CrossRef J. McNeill, M. Coln, B. Larivee, “A split-ADC architecture for deterministic digital background calibration of a 16b 1 MS/s ADC,” Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International, vol.48, 6–10, pp.276–598, Feb. 2005.CrossRef
19.
Zurück zum Zitat Y. Chiu, C.W. Tsang, B. Nikolic, P.R. Gray, “Least mean square adaptive digital background calibration of pipelined analog-to-digital converters,” IEEE TCAS-I, vol.51, pp.38–46, Jan. 2004.CrossRef Y. Chiu, C.W. Tsang, B. Nikolic, P.R. Gray, “Least mean square adaptive digital background calibration of pipelined analog-to-digital converters,” IEEE TCAS-I, vol.51, pp.38–46, Jan. 2004.CrossRef
20.
Zurück zum Zitat I. Ahmed, D.A. Johns, “An 11-Bit 45 MS/s pipelined ADC with rapid calibration of DAC errors in a multibit pipeline stage,” IEEE Journal of Solid-State Circuits, vol.43, no.7, pp.1626–1637, Jul. 2008.CrossRef I. Ahmed, D.A. Johns, “An 11-Bit 45 MS/s pipelined ADC with rapid calibration of DAC errors in a multibit pipeline stage,” IEEE Journal of Solid-State Circuits, vol.43, no.7, pp.1626–1637, Jul. 2008.CrossRef
21.
Zurück zum Zitat B. Murmann et al., “A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification,” IEEE Journal of Solid-State Circuits, vol.38, pp.2040–2050, Dec. 2003.CrossRef B. Murmann et al., “A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification,” IEEE Journal of Solid-State Circuits, vol.38, pp.2040–2050, Dec. 2003.CrossRef
22.
Zurück zum Zitat J.A. McNeill, S. Goluguri, A. Nair, “Split-ADC” digital background correction of open-loop residue amplifier nonlinearity errors in a 14b pipeline ADC,” IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007, vol., no. 27–30, pp.1237–1240, May 2007. J.A. McNeill, S. Goluguri, A. Nair, “Split-ADC” digital background correction of open-loop residue amplifier nonlinearity errors in a 14b pipeline ADC,” IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007, vol., no. 27–30, pp.1237–1240, May 2007.
23.
Zurück zum Zitat I. Ahmed, J. Mulder, D.A. Johns, “A 50MS/s 9.9 mW pipelined ADC with 58dB SNDR in 0.18um CMOS using capacitive charge-pumps,” Solid-State Circuits Conference, 2009. Digest of Technical Papers. ISSCC. 2009 IEEE International, vol.52, 9–12, pp.164–165, Feb. 2009.CrossRef I. Ahmed, J. Mulder, D.A. Johns, “A 50MS/s 9.9 mW pipelined ADC with 58dB SNDR in 0.18um CMOS using capacitive charge-pumps,” Solid-State Circuits Conference, 2009. Digest of Technical Papers. ISSCC. 2009 IEEE International, vol.52, 9–12, pp.164–165, Feb. 2009.CrossRef
24.
Zurück zum Zitat P. Quinn, M. Pribytko, “Capacitor matching insensitive 12-b 3.3 MS/s algorithmic ADC in 0.25/spl mu/m CMOS,” Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003, vol.21–24, pp.425–428, Sep. 2003.CrossRef P. Quinn, M. Pribytko, “Capacitor matching insensitive 12-b 3.3 MS/s algorithmic ADC in 0.25/spl mu/m CMOS,” Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003, vol.21–24, pp.425–428, Sep. 2003.CrossRef
Metadaten
Titel
Pipelined ADC Digital Calibration Techniques and Tradeoffs
verfasst von
Imran Ahmed
Copyright-Jahr
2010
Verlag
Springer Netherlands
DOI
https://doi.org/10.1007/978-90-481-3083-2_2

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