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Über dieses Buch

This book describes analytical models and estimation methods to enhance performance estimation of pipelined multiprocessor systems-on-chip (MPSoCs). A framework is introduced for both design-time and run-time optimizations. For design space exploration, several algorithms are presented to minimize the area footprint of a pipelined MPSoC under a latency or a throughput constraint. A novel adaptive pipelined MPSoC architecture is described, where idle processors are transitioned into low-power states at run-time to reduce energy consumption. Multi-mode pipelined MPSoCs are introduced, where multiple pipelined MPSoCs optimized separately are merged into a single pipelined MPSoC, enabling further reduction of the area footprint by sharing the processors and communication buffers. Readers will benefit from the authors’ combined use of analytical models, estimation methods and exploration algorithms and will be enabled to explore billions of design points in a few minutes.

Inhaltsverzeichnis

Frontmatter

Chapter 1. Introduction

This chapter of the monograph entails an overview of trends and challenges in multimedia applications and embedded architectures, starting from low resolution video processing on uniprocessor systems to high definition video processing on (heterogeneous) multiprocessor systems.

Haris Javaid, Sri Parameswaran

Chapter 2. Literature Survey

This chapter provides the necessary literature survey, focusing on homogeneous and heterogeneous MPSoCs, design space exploration techniques such as linear programming and heuristics, and run-time resource and power management techniques for MPSoCs.

Haris Javaid, Sri Parameswaran

Chapter 3. Optimisation Framework

This chapter provides a philosophical overview of the research reported in this monograph. Firstly, the application model and pipelined MPSoCs considered in this monograph are described. Then, shortcomings of prior research on pipelined MPSoCs are discussed in order to provide an idea of how this monograph fills in some of the gaps in prior research. Lastly, this chapter rationalises the design-time and run-time optimisations proposed for pipelined MPSoCs in this monograph.

Haris Javaid, Sri Parameswaran

Chapter 4. Performance Estimation of Pipelined MPSoCs

This chapter focuses on analytical models and estimation methods for three performance metrics (execution time, latency and throughput) of pipelined MPSoCs to speed up their design space exploration process.

Haris Javaid, Sri Parameswaran

Chapter 5. Design Space Exploration of Pipelined MPSoCs

A pipelined MPSoC’s stages need to be balanced for maximal utilisation of the processors to achieve high throughput with reduced area footprint and reduced power consumption. This chapter addresses the problem of optimising a pipelined MPSoC’s area footprint.

Haris Javaid, Sri Parameswaran

Chapter 6. Adaptive Pipelined MPSoCs

Pipelined MPSoCs optimised at design-time lack adaptability to run-time variations, and hence suffer from inefficient resource utilisation and may result in high energy consumption under a dynamic workload. This chapter proposes a novel adaptive pipelined MPSoC architecture, and a run-time processor manager for it.

Haris Javaid, Sri Parameswaran

Chapter 7. Power Management in Adaptive Pipelined MPSoCs

System-level power management schemes are often deployed in MPSoCs to exploit the idleness of processors at run-time for energy reduction by putting idle processors in low-power states [

1

,

2

]. These schemes decide “when" and “which" power state should be selected for a processor to maximally reduce the energy consumption of the MPSoC. The decision is a challenging one due to the latency and energy overheads involved in a transition from one power state to another. The aim of this chapter is to propose a power manager for an adaptive pipelined MPSoC to select the most suitable power state for each of the idle auxiliary processors.

Haris Javaid, Sri Parameswaran

Chapter 8. Multi-mode Pipelined MPSoCs

A pipelined MPSoC will typically be used as a multimedia accelerator because it is extremely customised for a specific multimedia application. The aim of this chapter is to reduce area footprint of pipelined MPSoCs based accelerators by combining multiple pipelined MPSoCs into a single multi-mode pipelined MPSoC.

Haris Javaid, Sri Parameswaran

Chapter 9. Conclusions and Future Work

This monograph explored implementation of multimedia applications on pipelined MultiProcessor System-on-Chip (MPSoC) architectures, and proposed design-time and run-time optimisations for area footprint and energy consumption. This chapter concludes the monograph with possible future work.

Haris Javaid, Sri Parameswaran

Backmatter

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