PLD Based Design with VHDL

Frontmatter

Chapter 1. Introduction to HDL

Abstract

This chapter discusses the digital logic design evolution and the basic ASIC design flow. The chapter describes the necessity of ASIC SOC prototype. The comparison of ASIC and FPGA implementation is described in this chapter. The chapter even discusses the need of HDL and VHDL different modeling styles using the small gate count example. This chapter is useful to the HDL beginners to understand about the difference between high-level language and HDL modeling styles.

Vaibbhav Taraate

Chapter 2. Basic Logic Circuits and VHDL Description

Abstract

This chapter describes the overview of various combinational logic elements. The chapter is organized in such a way that reader will be able to understand the concept of synthesizable RTL for the logic gates and small gate count combinational designs using synthesizable VHDL constructs. This chapter describes the basic logic gates, adders, gray-to-binary and binary-to-gray code converters. This chapter also covers the key practical concepts while designing by using the combinational logic elements.

Vaibbhav Taraate

Chapter 3. VHDL and Key Important Constructs

Abstract

This chapter discusses the key important VHDL constructs. VHDL a is hardware description language and consists of many powerful concurrent and sequential constructs. The key concurrent and sequential constructs are used to describe the design functionality to generate intended hardware. These constructs include process, when else, with select, if then else case, signal and variable declarations and assignments. Even this chapter discusses the important constructs like wait, wait on, wait for, wait until, for loop, and while loop. This chapter is useful for RTL design engineers to understand the VHDL coding styles and synthesizable VHDL. This chapter covers the practical illustrations for every construct. The explanation is given for every synthesizable VHDL code with the synthesis results. This can be useful while working in the FPGA as well as ASIC design domains.

Vaibbhav Taraate

Chapter 4. Combinational Logic Design Using VHDL Constructs

Abstract

This chapter discusses the RTL coding and synthesis using VHDL for the key combinational arithmetic resources such as adders, subtractors, multipliers, and comparators. This chapter is useful for the beginners to understand about the use of the concurrent and sequential VHDL constructs such as process, if then else, case, and their use in the design of combinational logic. Even this chapter discusses the code converters, data selectors as multiplexers, decoders, and encoders. This chapter is organized in such a way that it covers simple logic design and gate delay concepts to the priority logic design. This chapter concludes with the summary.

Vaibbhav Taraate

Chapter 5. Sequential Logic Design

Abstract

This chapter describes the practical understanding about the sequential logic designs. RTL coding using VHDL is described in detail with the practical scenarios and concepts. The VHDL RTL for the flip-flops, latches, various counters, and shift registers is covered with the synthesis results and explanations. Even this chapter describes the timing parameters for the sequential logic and the maximum frequency calculation for the design. The practical do’s and don’ts are explained with the meaningful diagrams and timing sequences. This chapter is useful for the ASIC and FPGA designers while coding for the sequential logic. This chapter also covers the asynchronous sequential circuits and issues like metastability in the design. How to overcome the metastability is explained with meaningful example and design scenarios.

Vaibbhav Taraate

Chapter 6. Introduction to PLD

Abstract

This chapter describes the practical understanding about the PLD architecture and the practical use in the ASIC prototyping and FPGA based design. This chapter is organized in such a way that it explains the PLD evolution and the classification with the detailed architecture. Even this chapter covers the practical scenarios while using the FPGA for prototyping. The architecture for XILINX and Altera is covered with the practical-oriented examples and the synthesis results.

Vaibbhav Taraate

Chapter 7. Design and Simulation Using VHDL Constructs

Abstract

This chapter discusses the VHDL constructs and their use during the design verification. The constructs such as subprogram, procedures, functions, TEXTIO, and file handling are discussed in this chapter with the practical examples. Even this chapter gives basic understanding of design simulation using the VHDL constructs. How to write an efficient testbench and how to carry out the presynthesis simulation are explained in this chapter with the simulation results. This chapter even discusses the use of the packages and file handling.

Vaibbhav Taraate

Chapter 8. PLD-Based Design Guidelines

Abstract

This chapter describes the design guidelines for ASIC and FPGA designs. The coding and design guidelines are useful in the RTL design cycle and recommended to be used for the efficient performance of the design. The design guidelines such as resource sharing, pipelining, logic duplications, grouping, use of signals and variables, gated clock, and clock enable logic are discussed in this chapter. Designers are requested to use these guidelines for area, speed, and power improvement in the design.

Vaibbhav Taraate

Chapter 9. Finite-State Machines

Abstract

This chapter describes the efficient FSM coding using VHDL constructs. The FSMs are of two types: Moore and Mealy, and this chapter focuses on the RTL design for the Moore and Mealy machines. Even this chapter discusses about the different encoding methods for FSM, and the FSM examples are described using binary, gray, and one-hot encoding method. The examples such as sequence detector and parity checker are useful in the real practical world and are discussed in this chapter. Even this chapter is useful to understand the importance of the multiple process FSM. The key design guidelines for FSM are described with the performance improvement techniques.

Vaibbhav Taraate

Chapter 10. Synthesis Optimization Using VHDL

Abstract

The PLD-based designs can be described by using concurrent and sequential VHDL constructs. In the practical scenario, the objective is to describe the design functionality by using synthesizable VHDL constructs and that can be accomplished by using important combinational and sequential design guidelines. This chapter focuses on the designs such as ALU, parity checkers, generators, memories, multipliers, and barrel shifters. This chapter also discusses about the synthesis result with the data path and control paths. The synthesis optimization techniques are discussed for the better synthesis outcome and used during RTL design cycle. This chapter is useful for ASIC and FPGA designers to understand the design using VHDL, critical paths and optimizations, and registered inputs and outputs. Even this chapter discusses about the synthesis outcome using Altera and Xilinx PLDs.

Vaibbhav Taraate

Chapter 11. Design Implementation Using Xilinx Vivado

Abstract

The PLD-based designs can be implemented by using the FPGA and by using the vendor-specific EDA tool chain. The chapter discusses about the design implementation using XILINX Vivado. The design flow using XILINX Vivado to perform the design simulation, synthesis, and implementation is discussed with the case study. Even this chapter discusses about the FIFO depth calculations and FIFO design.

Vaibbhav Taraate

Erratum to: PLD Based Design with VHDL

Vaibbhav Taraate

Backmatter