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Erschienen in:
Low Power Design: An Introduction Kapitel lesen Erstes Kapitel lesen

2010 | OriginalPaper | Buchkapitel

3. Power-efficient Processor Architecture

verfasst von : Dr. Preeti Ranjan Panda, Aviral Shrivastava, B. V. N. Silpa, Krishnaiah Gummidipudi

Erschienen in: Power-efficient System Design

Verlag: Springer US

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Abstract

Since the creation of the first processor/CPU in 1971, silicon technology consistently allowed to pack twice the number of transistors on the same die every 18 to 24 months [33]. Scaling of technology allowed the implementation of faster and larger circuits on silicon, permitting a sophisticated and powerful set of features to be integrated into CPU. Figure 3.1 shows the evolution of processors from 4-bit scalar datapath to 64-bit superscalar datapath and their respective transistor counts. Processors evolved not only in terms of datapath width, but also in terms of a wide variety of architectural features such as pipelining, floating point support, on-chip memories, superscalar processing, out-of-order processing, speculative execution, multi-threading, muticore CPUs, etc.

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Vorheriges Kapitel Basic Low Power Digital Design
Nächstes Kapitel Power-efficient Memory and Cache
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Metadaten
Titel
Power-efficient Processor Architecture
verfasst von
Dr. Preeti Ranjan Panda
Aviral Shrivastava
B. V. N. Silpa
Krishnaiah Gummidipudi
Copyright-Jahr
2010
Verlag
Springer US
Buch
Power-efficient System Design

Print ISBN: 978-1-4419-6387-1

Electronic ISBN: 978-1-4419-6388-8

Copyright-Jahr: 2010

DOI
https://doi.org/10.1007/978-1-4419-6388-8_3

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