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Erschienen in:
Introduction Kapitel lesen Erstes Kapitel lesen

2015 | OriginalPaper | Buchkapitel

2. Preliminaries

verfasst von : Mehdi Dehbashi, Görschwin Fey

Erschienen in: Debug Automation from Pre-Silicon to Post-Silicon

Verlag: Springer International Publishing

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Abstract

Each combinational circuit is represented by a directed acyclic graph C = (V, E), referred to as the circuit graph, where V is the set of circuit nodes and E ⊆ V × V, the set of edges, corresponds to the gate input-output connections in the circuit [LRS89]. For gate-level benchmarks, we consider the nodes to be gates with symmetric functions. Each node in the circuit graph is associated with a symmetric function which represents the corresponding behavior of that gate in the circuit. A symmetric function does not depend on the order of inputs but only on the sum of variables assigned to 0 or to 1, respectively.

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Vorheriges Kapitel Introduction
Nächstes Kapitel Automated Debugging for Logic Bugs
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Metadaten
Titel
Preliminaries
verfasst von
Mehdi Dehbashi
Görschwin Fey
Copyright-Jahr
2015
Buch
Debug Automation from Pre-Silicon to Post-Silicon

Print ISBN: 978-3-319-09308-6

Electronic ISBN: 978-3-319-09309-3

Copyright-Jahr: 2015

DOI
https://doi.org/10.1007/978-3-319-09309-3_2

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