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This book describes a new type of computer aided VLSI design tool, called a VLSI System Planning, that is meant to aid designers dur­ ing the early, or conceptual, state of design. During this stage of design, the objective is to define a general design plan, or approach, that is likely to result in an efficient implementation satisfying the initial specifications, or to determine that the initial specifications are not realizable. A design plan is a collection of high level design decisions. As an example, the conceptual design of digital filters involves choosing the type of algorithm to implement (e. g. , finite impulse response or infinite impulse response), the type of polyno­ mial approximation (e. g. , Equiripple or Chebyshev), the fabrication technology (e. g. , CMOS or BiCMOS), and so on. Once a particu­ lar design plan is chosen, the detailed design phase can begin. It is during this phase that various synthesis, simulation, layout, and test activities occur to refine the conceptual design, gradually filling more detail until the design is finally realized. The principal advantage of VLSI System Planning is that the increasingly expensive resources of the detailed design process are more efficiently managed. Costly redesigns are minimized because the detailed design process is guided by a more credible, consistent, and correct design plan.



Chapter 1. Introduction

During the course of the design process, a number of high-level decisions are typically made. For example, consider the design of an analog-to-digital converter. There are several options for the conversion algorithm, such as flash, successive approximation, dual slope integration, switch capacitor, etc. Once the conversion algorithm is selected, the logic and circuit design of the various computational units (e.g., counters, encoders, comparators, etc.) must be performed. Again, there are design decisions. Looking at a counter, there are several approaches to realizing the next state decoder and memory (e.g., RS flip-flop, JK flip-flop, etc.). In addition, a wide variety of fabrication technologies are available, such as CMOS (complementary metal-oxide semiconductor), STTL (Schottky transistor transistor logic), ECL (emitter-coupled logic), etc. These high-level decisions have a substantial impact on the performance of the finished product. Taken collectively, we call these decisions the design plan. In general, there can be an extremely large number of design plans that could yield designs that satisfied a set of initial functional specifications, but with greatly varying performance in terms of area, power dissipation, etc. Thus, each design plan results in a design that has a different set of tradeoffs.
Allen M. Dewey, Stephen W. Director

Chapter 2. Alternatives Exploration

As mentioned in the previous chapter, it is not the intent of the VLSI System Planning methodology to totally automate the planning process. Rather, the intent is to build a CAD tool that can effectively present, in an organized and logical fashion, the sizable amount of information required to enable the designer to make the key design decisions in developing a plan. To that end, this chapter and the following chapter will present the details of the general VLSI System Planning methodology. Before we begin our explanation of the VLSI System Planning methodology, it is perhaps useful to present an overview of the methodology to orient the reader and motivate the organization of the following material.
Allen M. Dewey, Stephen W. Director

Chapter 3. Design Assistance

The previous chapter explained the part of the VLSI System Planning methodology that provides the basic framework for formalizing the early decision-making processes of design. We discussed a means of conceptualizing or modeling the design process as a hierarchy of design issues and the important aspects of exploring the various design issues, such as constraints, delaying decisions, and backtracking. We now discuss the remaining part of the VLSI System Planning methodology illustrated in Figure 2.1, requesting assistance.
Allen M. Dewey, Stephen W. Director

Chapter 4. General Software Architecture

Having discussed the general VLSI System Planning methodology in Chapters 2 and 3, we now discuss the software architecture required to automate the methodology. This chapter will focus on the salient features from a conceptual or functional point of view. Supporting details on how the features are implemented are given in Appendix B.
Allen M. Dewey, Stephen W. Director

Chapter 5. A DSP VLSI System Planner

In essence, the VLSI System Planning methodology acts as a framework for formalizing the decision-making process of design[105]. In the previous chapters we explained the methodology by presenting several design examples, such as an analog-to-digital converter, a memory subsystem, a finite state machine, an analog amplifier, etc. The objective of this chapter is to present in more detail the application of the VLSI System Planning methodology to the task of designing digital signal processing (DSP) filters. There are two reasons for presenting this example. The first reason is to show how the complex and diverse facets of digital filter design can be enumerated and consolidated into a more organized and logical process by using the VLSI System Planning methodology. Secondly, in a broader context, the digital filter design application is also intented to convey the “mindset”, or line of reasoning, involved in studying a design process, modeling the process as a hierarchy of design issues, delineating the options, and identifying the associated interdependencies and discriminating characteristics so that the reader may apply the VLSI System Planning methodology to his particular design task of
Table 5.1
Digital Filter Design Issues
Design Issues
Filter Algorithms
Filter Architectures
Multiplier Logic Designs
Adder Logic Designs
Layout Design Styles
Fabrication Technologies
Allen M. Dewey, Stephen W. Director

Chapter 6. A DSP Prediction Methodology

The objective of this chapter is to illustrate the application of the general prediction methodology concepts discussed in Section 3.2 by explaining how the implementation performance predictions are obtained for the case of digital filter design. Based on the initial functional specifications and a high-level roadmap for how the design is to proceed, i.e., the design plan, we seek to predict the eventual implementation performance.
Allen M. Dewey, Stephen W. Director

Chapter 7. Yoda: Sample Planning Session

The objective of this chapter is to bring together the general VLSI System Planning concepts discussed in Chapters 1 through 4 and the specific details of the digital signal processing planner discussed in Chapters 5 and 6 by presenting a sample planning session with Yoda. The discussion of the sample planning session will be supported by figures illustrating the content of the terminal screen. In this manner, some “user-oriented” features of Yoda will also be explained. It should be noted that the figures illustrating the terminal screen are intended to convey the general nature of the Mx display. Hence, the figures do not include all the details of the screen about the various menus and windows.
Allen M. Dewey, Stephen W. Director

Chapter 8. Summary

The design of today’s integrated circuits is becoming complex enough to warrant the development of a planning capability whereby the possible courses of action and the associated consequences are investigated before undertaking the design and fabrication process. The number of options or alternatives and the associated maze of interdependencies has increased to the point that the decision-making process is quickly becoming unmanageable. The designer can no longer do the critical analysis in his head and the expense of executing the design process precludes the designer from finding a solution on a “trial-and-error” basis.
Allen M. Dewey, Stephen W. Director


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