Progress Towards a Systolic SVD Array Implementation

The past five years have seen a great deal of interest in parallel architectures for the computation of the singular value decomposition. We present a linear array approach which is unique in that there is no angle computation within the array, I/O time is balanced with computation time, communication is nearest neighbor, and simple multiply and accumulate processors are utilized. In addition, special properties of the SVD algorithm are exploited in order to obtain a VLSI design with reduced area. We are currently designing a chip using two micron CMOS design rules. When completed we estimate that our array will compute the SVD at a rate of between 5n and 10n MFlops/second, where n is the dimension of the array.