Skip to main content

2010 | OriginalPaper | Buchkapitel

2. PSP-SOI: A Surface-Potential-Based Compact Model of SOI MOSFETs

verfasst von : Weimin Wu, Wei Yao, Gennady Gildenblat

Erschienen in: Compact Modeling

Verlag: Springer Netherlands

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

Surface-potential-based models, which represent the mainstream approach to compact modeling of bulk MOSFETs, are now in the process of being applied to SOI devices. In this chapter we discuss two advanced SOI models—PSP-SOI-PD for partially depleted devices and PSP-SOI-DD including the dynamic depletion effects. Both models are based on the popular PSP model of bulk MOSFETs. The theoretical foundation of all PSP-family models is the symmetric linearization method that allows one to raise the physical contents of the compact model without prohibitive increase in its computational complexity. In addition to the physics-based structure of the new models inherited from bulk PSP, they account for phenomena specific to SOI devices (e.g. floating body, and valence band tunneling current) and include a detailed description of parasitic effects. We discuss both the theoretical developments and verification of the model against test data and TCAD simulations with particular emphasis on the interplay between the model structure and its simulation capabilities.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Literatur
1.
Zurück zum Zitat Anil, K.G., Mahapatra, S., Eisele, I.: Role of inversion layer quantization on sub-bandgap impact ionization in deep-sub-micron n-channel MOSFETs. In: IEDM Tech. Dig., pp. 675–678 (2000) Anil, K.G., Mahapatra, S., Eisele, I.: Role of inversion layer quantization on sub-bandgap impact ionization in deep-sub-micron n-channel MOSFETs. In: IEDM Tech. Dig., pp. 675–678 (2000)
2.
Zurück zum Zitat Bolouki, S., Maddah, M., Afzali-Kusha, A., El Nokali, M.: A unified IV model for PD/FD SOI MOSFETs with a compact model for floating body effects. Solid-State Electron. 47(11), 1909–1915 (2003) CrossRef Bolouki, S., Maddah, M., Afzali-Kusha, A., El Nokali, M.: A unified IV model for PD/FD SOI MOSFETs with a compact model for floating body effects. Solid-State Electron. 47(11), 1909–1915 (2003) CrossRef
3.
Zurück zum Zitat Brews, J.R.: A charge-sheet model of the MOSFET. Solid-State Electron. 21, 345–355 (1978) CrossRef Brews, J.R.: A charge-sheet model of the MOSFET. Solid-State Electron. 21, 345–355 (1978) CrossRef
4.
Zurück zum Zitat Cai, J., Sah, C.T.: Gate tunneling currents in ultrathin oxide metal–oxide–silicon transistors. J. Appl. Phys. 89(4), 2272–2285 (2001) CrossRef Cai, J., Sah, C.T.: Gate tunneling currents in ultrathin oxide metal–oxide–silicon transistors. J. Appl. Phys. 89(4), 2272–2285 (2001) CrossRef
5.
Zurück zum Zitat Chatterjee, P.K., Leiss, J.E., Taylor, G.W.: A dynamic average model for the body effect in ion implanted short channel (L=1 μm) MOSFET’s. IEEE Trans. Electron Devices 28(5), 606–607 (1981) CrossRef Chatterjee, P.K., Leiss, J.E., Taylor, G.W.: A dynamic average model for the body effect in ion implanted short channel (L=1 μm) MOSFET’s. IEEE Trans. Electron Devices 28(5), 606–607 (1981) CrossRef
6.
Zurück zum Zitat Chen, T.L., Gildenblat, G.: Symmetric bulk charge linearization of charge-sheet MOSFET model. Electron. Lett. 37(12), 791–793 (2001) CrossRef Chen, T.L., Gildenblat, G.: Symmetric bulk charge linearization of charge-sheet MOSFET model. Electron. Lett. 37(12), 791–793 (2001) CrossRef
7.
Zurück zum Zitat Chen, J., Chan, T.Y., Ko, P.K., Hu, C.: Subbreakdown drain leakage current in MOSFET. IEEE Electron Device Lett. 8, 515–517 (1987) CrossRef Chen, J., Chan, T.Y., Ko, P.K., Hu, C.: Subbreakdown drain leakage current in MOSFET. IEEE Electron Device Lett. 8, 515–517 (1987) CrossRef
8.
Zurück zum Zitat Chen, Q., Suryagandh, S., Goo, J.S., An, J.X., Thuruthiyil, C., Icel, A.B.: Impact of gate induced drain leakage and impact ionization currents on hysteresis modeling of PD SOI circuits. In: Tech. Proc. Workshop on Compact Modeling, pp. 570–573 (2007) Chen, Q., Suryagandh, S., Goo, J.S., An, J.X., Thuruthiyil, C., Icel, A.B.: Impact of gate induced drain leakage and impact ionization currents on hysteresis modeling of PD SOI circuits. In: Tech. Proc. Workshop on Compact Modeling, pp. 570–573 (2007)
9.
Zurück zum Zitat Chen, Q., Wu, Z.Y., Su, R.Y.K., Goo, J.S., Thuruthiyil, C., Radwin, M., Subba, N., Suryagandh, S., Ly, T., Wason, V., An, J.X., Icel, A.B.: Extraction of self-heating free I-V curves including the substrate current of PD SOI MOSFETs. In: IEEE Int. Conf. on Microelectron. Test Structures, pp. 272–275 (2007) Chen, Q., Wu, Z.Y., Su, R.Y.K., Goo, J.S., Thuruthiyil, C., Radwin, M., Subba, N., Suryagandh, S., Ly, T., Wason, V., An, J.X., Icel, A.B.: Extraction of self-heating free I-V curves including the substrate current of PD SOI MOSFETs. In: IEEE Int. Conf. on Microelectron. Test Structures, pp. 272–275 (2007)
10.
Zurück zum Zitat Chuang, C.T., Joshi, R.V., Puri, R., Kim, K.: Design considerations of scaled sub-0.1 μm PD/SOI CMOS circuits. In: Proc. Int. Symp. on Quality Electron. Des., pp. 153–158 (2003) Chuang, C.T., Joshi, R.V., Puri, R., Kim, K.: Design considerations of scaled sub-0.1 μm PD/SOI CMOS circuits. In: Proc. Int. Symp. on Quality Electron. Des., pp. 153–158 (2003)
11.
Zurück zum Zitat Chuang, C.T., Puri, R.: Effects of gate-to-body tunneling current on PD/SOI CMOS latches. In: Proc. Int. Conf. Simul. of Semicond. Processes and Devices, pp. 291–294 (2003) Chuang, C.T., Puri, R.: Effects of gate-to-body tunneling current on PD/SOI CMOS latches. In: Proc. Int. Conf. Simul. of Semicond. Processes and Devices, pp. 291–294 (2003)
12.
Zurück zum Zitat Colinge, J.P.: Silicon-On-Insulator Technology: Materials to VLSI, 3rd edn. Springer, Berlin (2004) CrossRef Colinge, J.P.: Silicon-On-Insulator Technology: Materials to VLSI, 3rd edn. Springer, Berlin (2004) CrossRef
13.
Zurück zum Zitat Dessai, G., Dey, A., Gildenblat, G., Smit, G.D.J.: Symmetric linearization method for double-gate and surrounding-gate MOSFET models. Solid-State Electron. 53(5), 548–556 (2009) CrossRef Dessai, G., Dey, A., Gildenblat, G., Smit, G.D.J.: Symmetric linearization method for double-gate and surrounding-gate MOSFET models. Solid-State Electron. 53(5), 548–556 (2009) CrossRef
14.
Zurück zum Zitat Dessai, G., Wu, W., Gildenblat, G.: Compact charge model for independent-gate asymmetric DGFET. IEEE Trans. Electron Devices (submitted) Dessai, G., Wu, W., Gildenblat, G.: Compact charge model for independent-gate asymmetric DGFET. IEEE Trans. Electron Devices (submitted)
15.
Zurück zum Zitat Dieudonne, F., Jomaah, J., Balestra, F.: Gate-induced floating body effect excess noise in partially depleted SOI MOSFETs. IEEE Electron Device Lett. 23(12), 737–739 (2002) CrossRef Dieudonne, F., Jomaah, J., Balestra, F.: Gate-induced floating body effect excess noise in partially depleted SOI MOSFETs. IEEE Electron Device Lett. 23(12), 737–739 (2002) CrossRef
16.
Zurück zum Zitat Faccio, F., Anghinolfi, F., Heijne, E.H.M., Jarron, P., Cristoloveanu, S.: Noise contribution of the body resistance in partially-depleted SOI MOSFETs. IEEE Trans. Electron Devices 45(5), 1033–1038 (1998) CrossRef Faccio, F., Anghinolfi, F., Heijne, E.H.M., Jarron, P., Cristoloveanu, S.: Noise contribution of the body resistance in partially-depleted SOI MOSFETs. IEEE Trans. Electron Devices 45(5), 1033–1038 (1998) CrossRef
17.
Zurück zum Zitat Fischetti, M.V., Sano, N., Laux, S.E., Natori, K.: Full-band Monte Carlo simulation of high-energy transport and impact ionization of electrons and holes in Ge, Si, and GaAs. In: Proc. Int. Conf. Simul. of Semicond. Processes and Devices, pp. 43–44 (1996) Fischetti, M.V., Sano, N., Laux, S.E., Natori, K.: Full-band Monte Carlo simulation of high-energy transport and impact ionization of electrons and holes in Ge, Si, and GaAs. In: Proc. Int. Conf. Simul. of Semicond. Processes and Devices, pp. 43–44 (1996)
18.
Zurück zum Zitat Getreu, I.E.: Modeling the Bipolar Transistor. Tektronix, Beaverton (1976) Getreu, I.E.: Modeling the Bipolar Transistor. Tektronix, Beaverton (1976)
19.
Zurück zum Zitat Gildenblat, G., Li, X., Wu, W., Wang, H., Jha, A., van Langevelde, R., Smit, G.D.J., Scholten, A.J., Klaassen, D.B.M.: PSP: an advanced surface-potential-based MOSFET model for circuit simulation. IEEE Trans. Electron Devices 53(9), 1979–1993 (2006) CrossRef Gildenblat, G., Li, X., Wu, W., Wang, H., Jha, A., van Langevelde, R., Smit, G.D.J., Scholten, A.J., Klaassen, D.B.M.: PSP: an advanced surface-potential-based MOSFET model for circuit simulation. IEEE Trans. Electron Devices 53(9), 1979–1993 (2006) CrossRef
20.
Zurück zum Zitat Gildenblat, G., Wang, H., Chen, T.L., Cai, X.: SP: an advanced surface-potential-based compact MOSFET model. IEEE J. Solid-State Circuits 39(9), 1394–1406 (2004) CrossRef Gildenblat, G., Wang, H., Chen, T.L., Cai, X.: SP: an advanced surface-potential-based compact MOSFET model. IEEE J. Solid-State Circuits 39(9), 1394–1406 (2004) CrossRef
21.
Zurück zum Zitat Gildenblat, G., Zhu, Z., McAndrew, C.C.: Surface potential equation for bulk MOSFET. Solid-State Electron. 53(1), 11–13 (2009) CrossRef Gildenblat, G., Zhu, Z., McAndrew, C.C.: Surface potential equation for bulk MOSFET. Solid-State Electron. 53(1), 11–13 (2009) CrossRef
22.
Zurück zum Zitat Goo, J.S., Williams, R.Q., Workman, G.O., Chen, Q., Lee, S., Nowak, E.J.: Compact modeling and simulation of PD-SOI MOSFETs: current status and challenges. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 265–272 (2008) Goo, J.S., Williams, R.Q., Workman, G.O., Chen, Q., Lee, S., Nowak, E.J.: Compact modeling and simulation of PD-SOI MOSFETs: current status and challenges. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 265–272 (2008)
23.
Zurück zum Zitat Gu, X., Wang, H., Chen, T.L., Gildenblat, G.: Substrate current in surface-potential-based compact MOFET models. In: Tech. Proc. Nanotechnol. Conf., pp. 310–313 (2003) Gu, X., Wang, H., Chen, T.L., Gildenblat, G.: Substrate current in surface-potential-based compact MOFET models. In: Tech. Proc. Nanotechnol. Conf., pp. 310–313 (2003)
24.
Zurück zum Zitat Gu, X., Chen, T.L., Gildenblat, G., Workman, G.O., Veeraraghavan, S., Shapira, S., Stiles, K.: A surface potential-based compact model of n-MOSFET gate-tunneling current. IEEE Trans. Electron Devices 51(1), 127–135 (2004) CrossRef Gu, X., Chen, T.L., Gildenblat, G., Workman, G.O., Veeraraghavan, S., Shapira, S., Stiles, K.: A surface potential-based compact model of n-MOSFET gate-tunneling current. IEEE Trans. Electron Devices 51(1), 127–135 (2004) CrossRef
25.
Zurück zum Zitat Gummel, H.K., Poon, H.C.: An integral charge control model of bipolar transistors. Bell Syst. Tech. J. 49(5), 827–852 (1970) Gummel, H.K., Poon, H.C.: An integral charge control model of bipolar transistors. Bell Syst. Tech. J. 49(5), 827–852 (1970)
26.
Zurück zum Zitat Jang, S.L., Huang, B.R., Ju, J.J.: A unified analytical fully depleted and partially depleted SOI MOSFET model. IEEE Trans. Electron Devices 46(9), 1872–1876 (1999) Jang, S.L., Huang, B.R., Ju, J.J.: A unified analytical fully depleted and partially depleted SOI MOSFET model. IEEE Trans. Electron Devices 46(9), 1872–1876 (1999)
27.
Zurück zum Zitat Jin, W., Chan, P.C.H., Fung, S.K.H., Ko, P.K.: Shot-noise-induced excess low-frequency noise in floating-body partially depleted SOI MOSFET’s. IEEE Trans. Electron Devices 46(6), 1180–1185 (1999) CrossRef Jin, W., Chan, P.C.H., Fung, S.K.H., Ko, P.K.: Shot-noise-induced excess low-frequency noise in floating-body partially depleted SOI MOSFET’s. IEEE Trans. Electron Devices 46(6), 1180–1185 (1999) CrossRef
28.
Zurück zum Zitat Jin, W., Fung, S.K.H., Liu, W., Chan, P.C.H., Hu, C.: Self-heating characterization for SOI MOSFET based on AC output conductance. In: IEDM Tech. Dig., pp. 175–178 (1999) Jin, W., Fung, S.K.H., Liu, W., Chan, P.C.H., Hu, C.: Self-heating characterization for SOI MOSFET based on AC output conductance. In: IEDM Tech. Dig., pp. 175–178 (1999)
29.
Zurück zum Zitat Joshi, R.V., Chuang, C.T., Fung, S.K.H., Assaderaghi, F., Sherony, M., Yang, I., Shahidi, G.: Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM. In: Symp. on VLSI Technol. Dig. of Tech. Papers, pp. 75–76 (2001) Joshi, R.V., Chuang, C.T., Fung, S.K.H., Assaderaghi, F., Sherony, M., Yang, I., Shahidi, G.: Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM. In: Symp. on VLSI Technol. Dig. of Tech. Papers, pp. 75–76 (2001)
30.
Zurück zum Zitat Kusu, S., Ishimura, K., Ohyama, K., Miyoshi, T., Hori, D., Sadachika, N., Murakami, T., Ando, M., Mattausch, H.J., Miura-Mattausch, M., Baba, S., Ida, J.: Consistent dynamic depletion model of SOI-MOSFETs for device/circuit optimization. In: Proc. IEEE Int. SOI Conf., pp. 59–60 (2008) Kusu, S., Ishimura, K., Ohyama, K., Miyoshi, T., Hori, D., Sadachika, N., Murakami, T., Ando, M., Mattausch, H.J., Miura-Mattausch, M., Baba, S., Ida, J.: Consistent dynamic depletion model of SOI-MOSFETs for device/circuit optimization. In: Proc. IEEE Int. SOI Conf., pp. 59–60 (2008)
31.
Zurück zum Zitat Lemaitre, L., McAndrew, C.C., Hamm, S.: ADMS: automated device model synthesize. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 27–30 (2002) Lemaitre, L., McAndrew, C.C., Hamm, S.: ADMS: automated device model synthesize. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 27–30 (2002)
32.
Zurück zum Zitat Lim, H.K., Fossum, J.G.: Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFET’s. IEEE Trans. Electron Devices 30(10), 1244–1251 (1983) CrossRef Lim, H.K., Fossum, J.G.: Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFET’s. IEEE Trans. Electron Devices 30(10), 1244–1251 (1983) CrossRef
33.
Zurück zum Zitat Lu, P.F., Chuang, C.T., Ji, J., Wagner, L.F., Hsieh, C.M., Kuang, J.B., Hsu, L.L.C., Pelella, M.M., Chu, S.F.S. Jr., Anderson, C.J.: Floating-body effects in partially depleted SOI CMOS circuits. IEEE J. Solid-State Circuits 32(8), 1241–1253 (1997) CrossRef Lu, P.F., Chuang, C.T., Ji, J., Wagner, L.F., Hsieh, C.M., Kuang, J.B., Hsu, L.L.C., Pelella, M.M., Chu, S.F.S. Jr., Anderson, C.J.: Floating-body effects in partially depleted SOI CMOS circuits. IEEE J. Solid-State Circuits 32(8), 1241–1253 (1997) CrossRef
34.
Zurück zum Zitat Mallikarjun, C., Bhat, K.: Numerical and charge sheet models for thin-film SOI MOSFETs. IEEE Trans. Electron Devices 37(9), 2039–2051 (1990) CrossRef Mallikarjun, C., Bhat, K.: Numerical and charge sheet models for thin-film SOI MOSFETs. IEEE Trans. Electron Devices 37(9), 2039–2051 (1990) CrossRef
35.
Zurück zum Zitat McAndrew, C.C.: Practical modeling for circuit simulation. IEEE J. Solid-State Circuits 33(3), 439–448 (1998) CrossRef McAndrew, C.C.: Practical modeling for circuit simulation. IEEE J. Solid-State Circuits 33(3), 439–448 (1998) CrossRef
36.
Zurück zum Zitat McAndrew, C.C., Victory, J.J.: Accuracy of approximations in MOSFET charge models. IEEE Trans. Electron Devices 49(1), 72–81 (2002) CrossRef McAndrew, C.C., Victory, J.J.: Accuracy of approximations in MOSFET charge models. IEEE Trans. Electron Devices 49(1), 72–81 (2002) CrossRef
37.
Zurück zum Zitat Mercha, A., Rafi, J.M., Simoen, E., Augendre, E., Claeys, C.: “Linear kink effect” induced by electron valence band tunneling in ultrathin gate oxide bulk and SOI MOSFETs. IEEE Trans. Electron Devices 50(7), 1675–1682 (2003) CrossRef Mercha, A., Rafi, J.M., Simoen, E., Augendre, E., Claeys, C.: “Linear kink effect” induced by electron valence band tunneling in ultrathin gate oxide bulk and SOI MOSFETs. IEEE Trans. Electron Devices 50(7), 1675–1682 (2003) CrossRef
38.
Zurück zum Zitat Murakami, T., Ando, M., Sadachika, N., Yoshida, T., Miura-Mattausch, M.: Modeling of floating-body effect in silicon-on-insulator metal-oxide-silicon field-effect transistor with complete surface-potential-based description. Jpn. J. Appl. Phys. 47(4), 2556–2559 Murakami, T., Ando, M., Sadachika, N., Yoshida, T., Miura-Mattausch, M.: Modeling of floating-body effect in silicon-on-insulator metal-oxide-silicon field-effect transistor with complete surface-potential-based description. Jpn. J. Appl. Phys. 47(4), 2556–2559
39.
Zurück zum Zitat Nakayama, H., Su, P., Hu, C., Nakamura, H., Komatsu, H., Takeshita, K., Komatsu, Y.: Methodology of self-heating free parameter extraction and circuit simulation for SOI CMOS. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 381–384 (2001) Nakayama, H., Su, P., Hu, C., Nakamura, H., Komatsu, H., Takeshita, K., Komatsu, Y.: Methodology of self-heating free parameter extraction and circuit simulation for SOI CMOS. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 381–384 (2001)
40.
Zurück zum Zitat Ortiz-Conde, A., Garcia Sanchez, F.J., Schmidt, P.E., Sa-Neto, A.: The nonequilibrium inversion layer charge of the thin-film SOI MOSFET. IEEE Trans. Electron Devices 36(9), 1651–1656 (1989) CrossRef Ortiz-Conde, A., Garcia Sanchez, F.J., Schmidt, P.E., Sa-Neto, A.: The nonequilibrium inversion layer charge of the thin-film SOI MOSFET. IEEE Trans. Electron Devices 36(9), 1651–1656 (1989) CrossRef
41.
Zurück zum Zitat Pao, H.C., Sah, C.T.: Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistors. Solid-State Electron. 9, 927–937 (1966) CrossRef Pao, H.C., Sah, C.T.: Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistors. Solid-State Electron. 9, 927–937 (1966) CrossRef
43.
Zurück zum Zitat Sadachika, N., Kitamaru, D., Uetsuji, Y., Navarro, D., Yusoff, M.M., Ezaki, T., Mattausch, H.J., Miura-Mattausch, M.: Completely surface-potential-based compact model of the fully depleted SOI-MOSFET including short-channel effects. IEEE Trans. Electron Devices 53(9), 2017–2024 (2006) CrossRef Sadachika, N., Kitamaru, D., Uetsuji, Y., Navarro, D., Yusoff, M.M., Ezaki, T., Mattausch, H.J., Miura-Mattausch, M.: Completely surface-potential-based compact model of the fully depleted SOI-MOSFET including short-channel effects. IEEE Trans. Electron Devices 53(9), 2017–2024 (2006) CrossRef
44.
Zurück zum Zitat Scholten, A.J., Tiemeijer, L.F., van Langevelde, R., Havens, R.J., Zegers-van Duijnhoven, A.T.A., Venezia, V.C.: Noise modeling for RF CMOS circuit simulation. IEEE Trans. Electron Devices 50(3), 618–632 (2003) CrossRef Scholten, A.J., Tiemeijer, L.F., van Langevelde, R., Havens, R.J., Zegers-van Duijnhoven, A.T.A., Venezia, V.C.: Noise modeling for RF CMOS circuit simulation. IEEE Trans. Electron Devices 50(3), 618–632 (2003) CrossRef
45.
Zurück zum Zitat Scholten, A.J., Smit, G.D.J., Durand, M., van Langevelde, R., Klaassen, D.B.M.: The physical background of JUNCAP2. IEEE Trans. Electron Devices 53(9), 2098–2107 (2006) CrossRef Scholten, A.J., Smit, G.D.J., Durand, M., van Langevelde, R., Klaassen, D.B.M.: The physical background of JUNCAP2. IEEE Trans. Electron Devices 53(9), 2098–2107 (2006) CrossRef
46.
Zurück zum Zitat Shahidi, G.G., Ajmera, A., Assaderaghi, F., Bolam, R.J., Hovel, H., Leobandung, E., Rausch, W., Sadana, D., Schepis, D., Wagner, L.F., Wissel, L., Wu, K., Davari, B.: Device and circuit design issues in SOI technology. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 339–346 (1999) Shahidi, G.G., Ajmera, A., Assaderaghi, F., Bolam, R.J., Hovel, H., Leobandung, E., Rausch, W., Sadana, D., Schepis, D., Wagner, L.F., Wissel, L., Wu, K., Davari, B.: Device and circuit design issues in SOI technology. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 339–346 (1999)
47.
Zurück zum Zitat Simoen, E., Mercha, A., Claeys, C., Lukyanchikova, N.B., Garhar, N.: Electron valence band tunnelling induced excess Lorentzian noise in fully depleted SOI transistors. In: Proc. Eur. Solid-State Device Res. Conf., pp. 279–282 (2003) Simoen, E., Mercha, A., Claeys, C., Lukyanchikova, N.B., Garhar, N.: Electron valence band tunnelling induced excess Lorentzian noise in fully depleted SOI transistors. In: Proc. Eur. Solid-State Device Res. Conf., pp. 279–282 (2003)
48.
Zurück zum Zitat Sinitsky, D., Fung, S., Tang, S., Su, P., Chan, M., Ko, P., Hu, C.: A dynamic depletion SOI MOSFET model for SPICE. In: Symp. on VLSI Technol. Dig. of Tech. Papers, pp. 114–115 (1998) Sinitsky, D., Fung, S., Tang, S., Su, P., Chan, M., Ko, P., Hu, C.: A dynamic depletion SOI MOSFET model for SPICE. In: Symp. on VLSI Technol. Dig. of Tech. Papers, pp. 114–115 (1998)
49.
Zurück zum Zitat Sleight, J., Rios, R.: A continuous compact MOSFET model for fully- and partially-depleted SOI devices. IEEE Trans. Electron Devices 45(4), 821–825 (1998) CrossRef Sleight, J., Rios, R.: A continuous compact MOSFET model for fully- and partially-depleted SOI devices. IEEE Trans. Electron Devices 45(4), 821–825 (1998) CrossRef
50.
Zurück zum Zitat Smit, G.D.J., Scholten, A.J., Serra, N., Pijper, R.M.T., van Langevelde, R., Mercha, A., Gildenblat, G., Klaassen, D.B.M.: PSP-based compact FinFET model describing dc and RF measurements. In: IEDM Tech. Dig., pp. 1–4 (2006) Smit, G.D.J., Scholten, A.J., Serra, N., Pijper, R.M.T., van Langevelde, R., Mercha, A., Gildenblat, G., Klaassen, D.B.M.: PSP-based compact FinFET model describing dc and RF measurements. In: IEDM Tech. Dig., pp. 1–4 (2006)
51.
Zurück zum Zitat Su, L.T., Chung, J.E., Antoniadis, A.D., Goodson, K.E., Flik, M.I.: Measurement and modeling of self-heating in SOI nMOSFET’s. IEEE Trans. Electron Devices 41(1), 69–75 (1994) CrossRef Su, L.T., Chung, J.E., Antoniadis, A.D., Goodson, K.E., Flik, M.I.: Measurement and modeling of self-heating in SOI nMOSFET’s. IEEE Trans. Electron Devices 41(1), 69–75 (1994) CrossRef
52.
Zurück zum Zitat Su, P., Fung, S.K.H., Assaderaghi, F., Hu, C.: A body-contact SOI MOSFET model for circuit simulation. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 50–51 (1999) Su, P., Fung, S.K.H., Assaderaghi, F., Hu, C.: A body-contact SOI MOSFET model for circuit simulation. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 50–51 (1999)
53.
Zurück zum Zitat Su, P., Fung, S.K.H., Tang, S., Assaderaghi, F., Hu, C.: BSIMPD: a partial-depletion SOI MOSFET model for deep-submicron CMOS designs. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 197–200 (2000) Su, P., Fung, S.K.H., Tang, S., Assaderaghi, F., Hu, C.: BSIMPD: a partial-depletion SOI MOSFET model for deep-submicron CMOS designs. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 197–200 (2000)
54.
Zurück zum Zitat Su, P., Goto, K., Sugii, T., Hu, C.: Enhanced substrate current in SOI MOSFETs. IEEE Electron Device Lett. 23(5), 282–284 (2002) CrossRef Su, P., Goto, K., Sugii, T., Hu, C.: Enhanced substrate current in SOI MOSFETs. IEEE Electron Device Lett. 23(5), 282–284 (2002) CrossRef
55.
Zurück zum Zitat Su, P., Fung, S.K.H., Wyatt, P.W., Wan, H., Chan, M., Niknejad, A.M., Hu, C.: A unified model for partial-depletion and full-depletion SOI circuit designs: using BSIMPD as a foundation. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 241–244 (2003) Su, P., Fung, S.K.H., Wyatt, P.W., Wan, H., Chan, M., Niknejad, A.M., Hu, C.: A unified model for partial-depletion and full-depletion SOI circuit designs: using BSIMPD as a foundation. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 241–244 (2003)
56.
Zurück zum Zitat Tenbroek, B.M., Lee, M.S.L., Redman-White, W., Bunyan, R.J.T., Uren, M.J.: Impact of self-heating and thermal coupling on analog circuits in SOI CMOS. IEEE J. Solid-State Circuits 33(7), 1037–1046 (1998) CrossRef Tenbroek, B.M., Lee, M.S.L., Redman-White, W., Bunyan, R.J.T., Uren, M.J.: Impact of self-heating and thermal coupling on analog circuits in SOI CMOS. IEEE J. Solid-State Circuits 33(7), 1037–1046 (1998) CrossRef
57.
Zurück zum Zitat Tseng, Y.C., Huang, W.M., Mendicino, M., Monk, D.J., Welch, P.J., Woo, J.C.S.: Comprehensive study on low-frequency noise characteristics in surface channel SOI CMOSFETs and device design optimization for RF ICs. IEEE Trans. Electron Devices 48(7), 1428–1437 (2001) CrossRef Tseng, Y.C., Huang, W.M., Mendicino, M., Monk, D.J., Welch, P.J., Woo, J.C.S.: Comprehensive study on low-frequency noise characteristics in surface channel SOI CMOSFETs and device design optimization for RF ICs. IEEE Trans. Electron Devices 48(7), 1428–1437 (2001) CrossRef
58.
Zurück zum Zitat Tsividis, Y.: Operation and Modeling of the MOS Transistor, 2nd edn. McGraw-Hill, New York (1999) Tsividis, Y.: Operation and Modeling of the MOS Transistor, 2nd edn. McGraw-Hill, New York (1999)
59.
Zurück zum Zitat Tsu, R., Esaki, L.: Tunneling in a finite superlattice. Appl. Phys. Lett. 22(11), 562–564 (1973) CrossRef Tsu, R., Esaki, L.: Tunneling in a finite superlattice. Appl. Phys. Lett. 22(11), 562–564 (1973) CrossRef
61.
Zurück zum Zitat Victory, J., Zhu, Z., Zhou, Q., Wu, W., Gildenblat, G., Yan, Z., Cordovez, J., McAndrew, C.C., Anderson, F., Paassches, J.C.J., van Langevelde, R., Kolev, P., Cherne, R., Yao, C.: PSP-based scalable MOS varactor model. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 495–502 (2007) Victory, J., Zhu, Z., Zhou, Q., Wu, W., Gildenblat, G., Yan, Z., Cordovez, J., McAndrew, C.C., Anderson, F., Paassches, J.C.J., van Langevelde, R., Kolev, P., Cherne, R., Yao, C.: PSP-based scalable MOS varactor model. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 495–502 (2007)
62.
Zurück zum Zitat Vogelsong, R., Brzezinski, C.: Simulation of thermal effects in electrical systems. In: IEEE Appl. Power Electron. Conf. and Expos. (APEC), pp. 353–356 (1989) Vogelsong, R., Brzezinski, C.: Simulation of thermal effects in electrical systems. In: IEEE Appl. Power Electron. Conf. and Expos. (APEC), pp. 353–356 (1989)
63.
Zurück zum Zitat Wan, H., Xi, X., Niknejad, A., Hu, C.: BSIMSOI4.0 MOSFET Model. University of California, Berkeley, CA (2005) Wan, H., Xi, X., Niknejad, A., Hu, C.: BSIMSOI4.0 MOSFET Model. University of California, Berkeley, CA (2005)
64.
Zurück zum Zitat Wang, H., Chen, T.L., Gildenblat, G.: Quasi-static and non-quasi-static compact MOSFET models based on symmetric linearization of the bulk and inversion charges. IEEE Trans. Electron Devices 50(11), 2262–2272 (2003) CrossRef Wang, H., Chen, T.L., Gildenblat, G.: Quasi-static and non-quasi-static compact MOSFET models based on symmetric linearization of the bulk and inversion charges. IEEE Trans. Electron Devices 50(11), 2262–2272 (2003) CrossRef
65.
Zurück zum Zitat Ward, D.E., Dutton, R.W.: A charge-oriented model for MOS transistor capacitances. IEEE J. Solid-State Circuits 13, 703–708 (1978) CrossRef Ward, D.E., Dutton, R.W.: A charge-oriented model for MOS transistor capacitances. IEEE J. Solid-State Circuits 13, 703–708 (1978) CrossRef
66.
Zurück zum Zitat Workman, G.O., Fossum, J.G.: A comparative analysis of the dynamic behavior of BTG/SOI MOSFETs and circuits with distributed body resistance. IEEE Trans. Electron Devices 45(10), 2138–2145 (1998) CrossRef Workman, G.O., Fossum, J.G.: A comparative analysis of the dynamic behavior of BTG/SOI MOSFETs and circuits with distributed body resistance. IEEE Trans. Electron Devices 45(10), 2138–2145 (1998) CrossRef
67.
Zurück zum Zitat Workman, G.O., Fossum, J.G.: Physical noise modeling of SOI MOSFETs with analysis of the Lorentzian component in the low-frequency noise spectrum. IEEE Trans. Electron Devices 47(6), 1192–1201 (2000) CrossRef Workman, G.O., Fossum, J.G.: Physical noise modeling of SOI MOSFETs with analysis of the Lorentzian component in the low-frequency noise spectrum. IEEE Trans. Electron Devices 47(6), 1192–1201 (2000) CrossRef
68.
Zurück zum Zitat Wu, W., Chen, T.L., Gildenblat, G., McAndrew, C.C.: Physics-based mathematical conditioning of the MOSFET surface potential equation. IEEE Trans. Electron Devices 51(7), 1196–1199 (2004) CrossRef Wu, W., Chen, T.L., Gildenblat, G., McAndrew, C.C.: Physics-based mathematical conditioning of the MOSFET surface potential equation. IEEE Trans. Electron Devices 51(7), 1196–1199 (2004) CrossRef
69.
Zurück zum Zitat Wu, W., Li, X., Wang, H., Gildenblat, G., Workman, G.O., Veeraraghavan, S., McAndrew, C.C.: SP-SOI: a third generation surface potential based compact SOI MOSFET model. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 819–822 (2005) Wu, W., Li, X., Wang, H., Gildenblat, G., Workman, G.O., Veeraraghavan, S., McAndrew, C.C.: SP-SOI: a third generation surface potential based compact SOI MOSFET model. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 819–822 (2005)
70.
Zurück zum Zitat Wu, W., Li, X., Gildenblat, G., Workman, G., Veeraraghavan, S., McAndrew, C.C., van Langevelde, R., Smit, G.D.J., Scholten, A.J., Klaassen, D.B.M., Watts, J.: PSP-SOI: a surface potential based compact model of partially depleted SOI MOSFETs (invited). In: Proc. IEEE Custom Integr. Circuits Conf., pp. 41–48 (2007) Wu, W., Li, X., Gildenblat, G., Workman, G., Veeraraghavan, S., McAndrew, C.C., van Langevelde, R., Smit, G.D.J., Scholten, A.J., Klaassen, D.B.M., Watts, J.: PSP-SOI: a surface potential based compact model of partially depleted SOI MOSFETs (invited). In: Proc. IEEE Custom Integr. Circuits Conf., pp. 41–48 (2007)
71.
Zurück zum Zitat Wu, W., Li, X., Gildenblat, G., Workman, G.O., Veeraraghavan, S., Watts, J.: A nonlinear body resistance model for accurate PD/SOI technology characterization. In: Proc. IEEE Int. SOI Conf., pp. 151–152 (2008) Wu, W., Li, X., Gildenblat, G., Workman, G.O., Veeraraghavan, S., Watts, J.: A nonlinear body resistance model for accurate PD/SOI technology characterization. In: Proc. IEEE Int. SOI Conf., pp. 151–152 (2008)
72.
Zurück zum Zitat Wu, W., Li, X., Gildenblat, G., Workman, G.O., Veeraraghavan, S., McAndrew, C.C., van Langevelde, R., Smit, G.D.J., Scholten, A.J., Klaassen, D.B.M., Watts, J.: PSP-SOI: An advanced surface potential based compact model of partially depleted SOI MOSFETs for circuit simulations. Solid-State Electron. 53, 18–29 (2009) CrossRef Wu, W., Li, X., Gildenblat, G., Workman, G.O., Veeraraghavan, S., McAndrew, C.C., van Langevelde, R., Smit, G.D.J., Scholten, A.J., Klaassen, D.B.M., Watts, J.: PSP-SOI: An advanced surface potential based compact model of partially depleted SOI MOSFETs for circuit simulations. Solid-State Electron. 53, 18–29 (2009) CrossRef
74.
Zurück zum Zitat Yang, J.W., Fossum, J.G., Workman, G.O., Huang, C.L.: A physical model for gate-to-body tunneling current and its effects on floating-body PD/SOI CMOS devices and circuits. Solid-State Electron. 48(2), 259–270 (2004) CrossRef Yang, J.W., Fossum, J.G., Workman, G.O., Huang, C.L.: A physical model for gate-to-body tunneling current and its effects on floating-body PD/SOI CMOS devices and circuits. Solid-State Electron. 48(2), 259–270 (2004) CrossRef
75.
Zurück zum Zitat Yu, Y., Kim, S., Hwang, S., Ahn, D.: All-analytic surface potential model for SOI MOSFETs. IEE Proc. Circuits Device Syst. 152(2), 183–188 (2005) CrossRef Yu, Y., Kim, S., Hwang, S., Ahn, D.: All-analytic surface potential model for SOI MOSFETs. IEE Proc. Circuits Device Syst. 152(2), 183–188 (2005) CrossRef
Metadaten
Titel
PSP-SOI: A Surface-Potential-Based Compact Model of SOI MOSFETs
verfasst von
Weimin Wu
Wei Yao
Gennady Gildenblat
Copyright-Jahr
2010
Verlag
Springer Netherlands
DOI
https://doi.org/10.1007/978-90-481-8614-3_2

Neuer Inhalt