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Über dieses Buch

From the Foreword.....
Modern digital signal processing applications provide a large challenge to the system designer. Algorithms are becoming increasingly complex, and yet they must be realized with tight performance constraints. Nevertheless, these DSP algorithms are often built from many constituent canonical subtasks (e.g., IIR and FIR filters, FFTs) that can be reused in other subtasks. Design is then a problem of composing these core entities into a cohesive whole to provide both the intended functionality and the required performance.
In order to organize the design process, there have been two major approaches. The top-down approach starts with an abstract, concise, functional description which can be quickly generated. On the other hand, the bottom-up approach starts from a detailed low-level design where performance can be directly assessed, but where the requisite design and interface detail take a long time to generate. In this book, the authors show a way to effectively resolve this tension by retaining the high-level conciseness of VHDL while parameterizing it to get good fit to specific applications through reuse of core library components. Since they build on a pre-designed set of core elements, accurate area, speed and power estimates can be percolated to high- level design routines which explore the design space. Results are impressive, and the cost model provided will prove to be very useful. Overall, the authors have provided an up-to-date approach, doing a good job at getting performance out of high-level design.
The methodology provided makes good use of extant design tools, and is realistic in terms of the industrial design process. The approach is interesting in its own right, but is also of direct utility, and it will give the existing DSP CAD tools a highly competitive alternative. The techniques described have been developed within ARPAs RASSP (Rapid Prototyping of Application Specific Signal Processors) project, and should be of great interest there, as well as to many industrial designers.
Professor Jonathan Allen, Massachusetts Institute of Technology

Inhaltsverzeichnis

Frontmatter

1. Introduction

Abstract
This monograph proposes the rapid design synthesis of Application-Specific Integrated Circuits (ASICs) for Digital Signal Processing (DSP) from a given set of design specifications through the use of library of functional cores. ASICs are the method of choice in DSP, when very high sample rates are sought in combination with low power and area requirements. Their drawback in comparison with programmable DSPs has been their long design times (12–18 months), lack of easy upgrades for legacy ASICs, very little hardware design reuse via libraries of DSP modules, and little capability to combine algorithmic design with lower level implementation tradeoffs. The traditional approach to design ASICs has always been through the following iterative procedure:
1.
Customer requirements are documented.
 
2.
Vendor converts requirements to specifications.
 
3.
Vendor “trades off” a variety of possible implementations, selected manually or in an automated manner, that meet the specifications via simulation.
 
4.
Vendor synthesizes acceptable design, verifies functionality and timing, and reiterates through the design process if specifications are not met.
 
Mohamed S. Ben Romdhane, Vijay K. Madisetti, John W. Hines

2. Background

Abstract
This chapter reviews the background required for this monograph. First, common ASIC design approaches are introduced. Advantages and limitations of ASICs with regard to general-purpose DSP processors are outlined. Section 2.2 describes popular design approaches and environments proposed in recent literature to synthesize ASICs form HDL descriptions. In section 2.3, a comparison between existing ASIC design tools is proposed based on criteria such as — design turnaround, flexibility, ease-of-use, and performance. Section 2.4 introduces a cost model originally proposed by Synopsys and Xilinx that compares the ASIC and FPGA alternatives. This cost model and assumptions made will serve us later, when we compare our proposed design methodology with other high-level approaches.
Mohamed S. Ben Romdhane, Vijay K. Madisetti, John W. Hines

3. VHDL-Based Design

Abstract
Hardware design has recently undergone dramatic changes in design methodologies, especially with the proliferation of hardware description languages (HDLs) that promote the integration of the design methodology into a unified environment. Designs described in HDLs are kept at a more abstract level of representation than what traditional methods allow. HDL descriptions can take a variety of abstraction levels (See Figure 2.1). Synthesis is the step taken to translate the HDL description to a lower level of representation (i.e., the gate-level). Behavioral synthesis extracts an RTL (clock-level) structure from a behavioral HDL description. Practical approaches to behavioral synthesis set design restrictions (i.e., the use of pragmas in Mistral 2) in order to provide acceptable performance. While several HDLs exist, we recommend VHDL, which is also an IEEE standard (1076–1987/93).
Mohamed S. Ben Romdhane, Vijay K. Madisetti, John W. Hines

4. Design for Reuse

Abstract
This chapter starts with an introduction to the core-based DfR/DwR methodology proposed in this monograph. The issues involved in defining an efficient reuse-based design environment are investigated and defined. Later sections describe the different design views that constitute the proposed design methodology. A cost model that compares the relative costs for proposed and existing approaches to ASIC design is also presented.
Mohamed S. Ben Romdhane, Vijay K. Madisetti, John W. Hines

5. Design with Reuse

Abstract
This chapter describes the core-based design of a few ASICs using the proposed approach of earlier chapters. Applications of interest include a number of signal processors — FIR chips, FFT chips, and related ASICs and ASSPs.
Mohamed S. Ben Romdhane, Vijay K. Madisetti, John W. Hines

6. Board Integration

Abstract
Most ASICs fail within the board-level environment if the component interface clock-level timing and functionality is not considered early in the design process. Recent AT&T studies show that nearly 50% of ASICs fail at the system level. This chapter describes how core-based ASICs can be integrated into board-level designs.
Mohamed S. Ben Romdhane, Vijay K. Madisetti, John W. Hines

7. Conclusions

Abstract
Application Specific Integrated Circuits (ASICs) have kept pace pace with the increasing complexity of applications and their demands for higher data rates, though this situation seems ready to change. Estimates show that the capability (in terms of gates) to design efficiently would lag considerably behind the capability to manufacture ASICs. New factors that influence the design of ASICs are also to be taken into consideration. These include; deep submicron designs, developments in synthesis and top-down design using hardware description languages (HDLs), and increasing time-to-market pressures. The primary goal is to provide users with desirable features such as — flexibility, ease-of-use, high reuse, quick-turnaround, high performance, integrability, accuracy, portability, and reliability. Existing design methodologies and environments support a few of these desirable features (see section 2.3). The purpose of this monograph was to define a design methodology for ASSPs that provides a competitive advantage to an organization through the use of commercial-off-the shelf (COTS) CAD/ESDA design environments.
Mohamed S. Ben Romdhane, Vijay K. Madisetti, John W. Hines

Backmatter

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