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Journal of Electronic Testing
Erschienen in: Journal of Electronic Testing 2/2021

23.04.2021

Radiation Tolerant SRAM Cell Design in 65nm Technology

verfasst von: JianAn Wang, Xue Wu, Haonan Tian, Lixiang Li, Shuting Shi, Li Chen

Erschienen in: Journal of Electronic Testing | Ausgabe 2/2021

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Abstract

In this paper, eight different SRAM cells are studied and evaluated with a 65nm CMOS technology. The cells were designed with radiation-hardening-by-design approaches including schematic and layout techniques. The eight types of cells were placed into eight pages of an SRAM test chip. The alpha and proton irradiation demonstrated that the Dual Interlocked Cell (DICE) has the best radiation-tolerant performance, but requires the largest area. The 6T and 11T cells designed with charge cancellation techniques can reduce soft errors up to 2-3 times with less area overhead. Several DICE variants were developed with reduced area overhead and showed SEU resilience performance equivalent to DICE. Simulation results are also presented in this paper to validate the findings.
Vorheriger Artikel Tolerating Soft Errors with Horizontal-Vertical-Diagonal-N-Queen (HVDNQ) Parity
Nächster Artikel Soft Errors Sensitivity of SRAM Cells in Hold, Write, Read and Half-Selected Conditions

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Metadaten
Titel
Radiation Tolerant SRAM Cell Design in 65nm Technology
verfasst von
JianAn Wang
Xue Wu
Haonan Tian
Lixiang Li
Shuting Shi
Li Chen
Publikationsdatum
23.04.2021
Verlag
Springer US
Erschienen in
Journal of Electronic Testing / Ausgabe 2/2021
Print ISSN: 0923-8174
Elektronische ISSN: 1573-0727
DOI
https://doi.org/10.1007/s10836-021-05941-5

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