Random Number Generators

The design and implementation of random number generators (RNGs) have been widely studied during the last years to improve applications that require random sequences. The RNGs can be classified as true (TRNGs) or pseudo (PRNGs), and either or both can be designed by using different algorithms or hardware. This chapter shows the basics of PRNGs and introduces the ways they are implemented by using chaotic maps, chaotic systems, and fractional-order chaotic oscillators. The goal of the book is devoted to provide guidelines for the block descriptions of chaotic maps and systems, their Verilog descriptions, and their FPGA implementation. This chapter provides a general overview of the application of RNGs, their design using chaotic systems, and their hardware implementations.

Chaotic systems have shown advantages in a wide range of applications from noise signal generators up to secure communications and neuromorphic systems. Such applications include the use of chaotic maps and fractional-order chaotic systems that can generate self-excited and hidden attractors, and as described in Chap. 1, they can be implemented by using integrated circuit technology, commercially available electronic devices, microcontrollers, raspberry-Pi, and embedded hardware such as field-programmable analog arrays (FPAAs) and field-programmable gate arrays (FPGAs). In the implementations, numerical methods play an important role to guarantee chaotic behavior in a long time and to provide high throughput and maximize the operation frequency that can be achieved by using low hardware resources. This chapter shows the models of the chaotic systems that are case study in the following chapters and some numerical methods to solve integer- and fractional-order chaotic systems. The models consists of ordinary differential equations (ODEs) consisting of three (3D), four (4D), and five (5D) state variables. In particular, this book considers chaotic maps, the well-known Lorenz system, a multistable 3D memristive that is simulated in its integer- and fractional-order versions, and two hyperchaotic systems (4D and 5D). They are implemented on FPGA to design pseudo-random number generators (PRNGs), in Chaps. 5 and 6.

The chaotic systems described in the previous chapter can be simulated under a hardware description language, such as Verilog, and afterwards, the code can be synthesized into an FPGA. This chapter shows the Verilog descriptions of arithmetic and sequential blocks that are required to simulate chaotic maps and systems. Each block is detailed and is instantiated in the Verilog description of PRNGs based on chaotic maps and systems, as is shown in Chaps. 5 and 6. This chapter ends with the Verilog description of the equations modeling a 2D Sprott map and the 3D Lorenz system.

The randomness of binary sequences can be evaluated by performing statistical tests. This chapter describes three suits of statistical tests to probe if a sequence of binary 0 and 1 bits or a set of floating point numbers are random. Some examples are given as guidelines to know how the tests must be performed. It is worthy to mention that the NIST test suite only can be used to test sequences of binary numbers. The TestU01 suite can be used with both binary sequences and sequences of real numbers within the interval \([0,1)\). The third statistical test, Dieharder, can be used with binary numbers and needs a lot of sequences as explained in this chapter. A key point is that some test of Dieharder are already included in the TestU01 statistical suite.

This chapter describes the design of PRNGs using chaotic maps and chaotic systems. The first PRNG uses a 2D map and the second and third PRNGs use maps without fixed points and are simulated in fixed-point arithmetic. Analyzing the first PRNG, one can appreciate the advantage of using fixed-point arithmetic instead of floating-point numbers. The FPGA synthesis of the first PRNG is detailed along the Verilog description. The chapter follows describing NIST and TestU01 tests for the 3D Lorenz system, which is also synthesized into an FPGA along its Verilog description. The FPGA synthesis of PRNGs based on 4D and 5D chaotic systems is also described, and their experimental results are provided.

The solution of fractional-order chaotic systems can be performed by applying numerical methods that require past values, considered as the memory or history. Practically, any integer-order chaotic system can be transformed to a fractional-order one, and one can find several works doing this transformations as well as the FPGA implementation. In this chapter a fractional-order chaotic system based on a memristor with time delay is described. The Block Verilog descriptions are detailed to infer the usefulness of applying the short memory principle to save hardware resources. Experimental results are given for the FPGA implementation of a PRNG based on the fractional-order chaotic system based on a memristor with time delay. The hardware resources are also provided, so that one can compare the results with the FPGA implementation of integer-order chaotic systems, for instance.

Chaos-based cryptographic applications began from more than three decades ago. The seminal work of Louis M Pecora and Thomas Carroll in 1990 showed the synchronization in chaotic systems. It was a master-slave topology that was used to implement a secure communication system by performing the masking of information with chaotic time series. Nowadays, a huge number of works are cited this seminal chapter to introduce new secure communication systems that exploit the dynamical characteristics of chaotic maps and systems to generate pseudo-random binary sequences. In this manner, this chapter shows the use of the PRNGs designed in Chaps. 5 and 6 to encrypt color or RGB images. In addition, an FPGA implementation is described herein to authenticate encrypted images using chaos-based PRNGs. The authentication process is performed by using hash functions. The Verilog descriptions of the architecture are provided by using fixed-point format, as done in the previous chapters.