Real-Time System-on-a-Chip Emulation

The productivity gap between the designer and the opportunities for silicon integration places increasing pressure on system verification in particular. A comprehensive design flow for digital systems from high-level algorithmic specifications to FPGA-based emulation and final ASIC implementation is presented. The design is entered only using a component library with predictable performance, therefore, enabling rapid system development and easing the verification burden. Hardware emulation, from this description, enables rapid prototyping of large systems where gate-level simulations are impractical. The primary goal of the emulator is to support design space exploration of real-time algorithms. The design environment is customized towards low-power and data-flow dominant architectures, particularly focusing on applications related to wireless communications. The design process of a 1 Mbit/s transmission system is explored, demonstrating the design convenience and the early performance analysis.