Skip to main content
Erschienen in: Journal of Computational Electronics 4/2019

25.07.2019

Reduction of the kink effect in a SELBOX tunnel FET and its RF/analog performance

verfasst von: Puja Ghosh, Brinda Bhowmick

Erschienen in: Journal of Computational Electronics | Ausgabe 4/2019

Einloggen

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

The kink effect in a fully depleted silicon-on-insulator (SOI) tunnel field-effect transistor (TFET) is studied and compared with the results for a SOI metal–oxide–semiconductor field-effect transistor (MOSFET) using a model that is calibrated against experimental results available in literature. A technique for eliminating the kink effect is proposed. The structure with a small gap in the buried oxide, known as the selective buried oxide (SELBOX) structure, is capable of reducing the kink effect. The impact of the kink effect on the device performance for different gap positions, thicknesses, and buried oxide thicknesses is examined. A better current–voltage characteristic is obtained for a position of the gap near the source. The effect of varying the temperature and the presence of a uniform trap charge on the kink effect for the SOI TFET, SOI MOSFET, and SELBOX structures is also studied. Various electrical parameters such as the subthreshold swing and ION/IOFF ratio are investigated for the TFET in the presence and absence of uniform trap charge. Although the SELBOX structure can minimize the kink effect, it is still present for such devices with narrow and wider gaps. Therefore, the gap thickness is optimized based on technology computer-aided design (TCAD) simulations. Furthermore, radio frequency (RF)/analog performance parameters such as the transconductance (gm), cutoff frequency (ft), transconductance generation factor (TGF = gm/ID), transconductance frequency product, gain transconductance frequency product, and 1-dB compression point are investigated using TCAD simulations and compared between the SELBOX MOSFET and SELBOX TFET devices.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

Literatur
1.
Zurück zum Zitat Choi, W.Y., Park, B.-G., Lee, J.D., Liu, T.-J.K.: Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett. 28, 743–745 (2007)CrossRef Choi, W.Y., Park, B.-G., Lee, J.D., Liu, T.-J.K.: Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett. 28, 743–745 (2007)CrossRef
2.
Zurück zum Zitat Gandhi, R., Chen, Z., Singh, N., Banerjee, K., Lee, S.: Vertical Si-nanowire n-type tunneling FETs with low subthreshold swing (650 mV/decade) at room temperature. IEEE Electron Device Lett. 32, 437–439 (2011)CrossRef Gandhi, R., Chen, Z., Singh, N., Banerjee, K., Lee, S.: Vertical Si-nanowire n-type tunneling FETs with low subthreshold swing (650 mV/decade) at room temperature. IEEE Electron Device Lett. 32, 437–439 (2011)CrossRef
3.
Zurück zum Zitat Krishnamohan, T., Kim, D., Raghunathan, S., Saraswat, K.: Double-gate strained-Ge heterostructure. Tunneling FET (TFET) with record high drive currents and < 60 mV/dec subthreshold slope. In: IEEE Technical Digest–International Electron Devices Meeting, pp. 1–3 (2008) Krishnamohan, T., Kim, D., Raghunathan, S., Saraswat, K.: Double-gate strained-Ge heterostructure. Tunneling FET (TFET) with record high drive currents and < 60 mV/dec subthreshold slope. In: IEEE Technical Digest–International Electron Devices Meeting, pp. 1–3 (2008)
4.
Zurück zum Zitat Verhulst, A.S., Vandenberghe, W.G., Maex, K., Groeseneken, G.: Tunnel field-effect transistor without gate–drain overlap. Appl. Phys. Lett. 91, 1–3 (2007)CrossRef Verhulst, A.S., Vandenberghe, W.G., Maex, K., Groeseneken, G.: Tunnel field-effect transistor without gate–drain overlap. Appl. Phys. Lett. 91, 1–3 (2007)CrossRef
5.
Zurück zum Zitat Le, S.T., Jannaty, P., Luo, X., Zaslavsky, A., Perea, D.E., Dayeh, S.A., Picraux, S.T.: Axial SiGe heteronanowire tunneling field-effect transistors. Nano Lett. 12, 5850–5855 (2012)CrossRef Le, S.T., Jannaty, P., Luo, X., Zaslavsky, A., Perea, D.E., Dayeh, S.A., Picraux, S.T.: Axial SiGe heteronanowire tunneling field-effect transistors. Nano Lett. 12, 5850–5855 (2012)CrossRef
6.
Zurück zum Zitat Tsutsui, G., Saitoh, M., Nagumo, T., Hiramoto, T.: Impact of SOI thickness fluctuation on threshold voltage variation in ultra-thin body SOI MOSFETs. IEEE Trans. Nanotechnol. 4, 369–373 (2005)CrossRef Tsutsui, G., Saitoh, M., Nagumo, T., Hiramoto, T.: Impact of SOI thickness fluctuation on threshold voltage variation in ultra-thin body SOI MOSFETs. IEEE Trans. Nanotechnol. 4, 369–373 (2005)CrossRef
7.
Zurück zum Zitat Chander, S., Bhowmick, B., Baishya, S.: Heterojunction fully depleted SOI-TFET with oxide/source overlap. Superlattices Microstruct. 86, 43–50 (2015)CrossRef Chander, S., Bhowmick, B., Baishya, S.: Heterojunction fully depleted SOI-TFET with oxide/source overlap. Superlattices Microstruct. 86, 43–50 (2015)CrossRef
8.
Zurück zum Zitat Lee, M.J., Choi, W.Y.: Analytical model of single-gate silicon-on-insulator (SOI) tunneling field-effect transistors (TFETs). Solid State Electron. 63, 110–114 (2011)CrossRef Lee, M.J., Choi, W.Y.: Analytical model of single-gate silicon-on-insulator (SOI) tunneling field-effect transistors (TFETs). Solid State Electron. 63, 110–114 (2011)CrossRef
9.
Zurück zum Zitat Sen, J., Baishya, S., Bhowmick, B.: Optimisation and length scaling of raised drain buried oxide SOI tunnel FET. Electron. Lett. 49, 1031–1033 (2013)CrossRef Sen, J., Baishya, S., Bhowmick, B.: Optimisation and length scaling of raised drain buried oxide SOI tunnel FET. Electron. Lett. 49, 1031–1033 (2013)CrossRef
10.
Zurück zum Zitat Narayanan, M.R., Al-Nashash, H., Pal, D., Chandra, M., Yasmine Hammamet, T.: Frequency response of MOS devices with SELBOX structure. Presented at 2012 16th IEEE Mediterranean Electrotechnical Conference, pp. 1099–1102 (2012) Narayanan, M.R., Al-Nashash, H., Pal, D., Chandra, M., Yasmine Hammamet, T.: Frequency response of MOS devices with SELBOX structure. Presented at 2012 16th IEEE Mediterranean Electrotechnical Conference, pp. 1099–1102 (2012)
11.
Zurück zum Zitat Kuo, J.B., Lin, S.C.: Low-Voltage SOI CMOS VLSI Devices and Circuits. Wiley, New York (2001) Kuo, J.B., Lin, S.C.: Low-Voltage SOI CMOS VLSI Devices and Circuits. Wiley, New York (2001)
12.
Zurück zum Zitat Narayanan, M., Al-Nashash, H., Mazhari, B., Pal, D. Chandra, M.: Analysis of kink reduction in SOI MOSFET using selective back oxide structure. Active Passive Electron. Compon. Article ID 565827, 1–9 (2012) Narayanan, M., Al-Nashash, H., Mazhari, B., Pal, D. Chandra, M.: Analysis of kink reduction in SOI MOSFET using selective back oxide structure. Active Passive Electron. Compon. Article ID 565827, 1–9 (2012)
13.
Zurück zum Zitat Chen, J., Solomon, R., Chan, T.Y., Ko, P.K., Hu, C.: Threshold voltage and C–V characteristics of SOI MOSFET’s related to Si film thickness variation on SIMOX wafers. IEEE Trans. Electron Devices 39, 2346–2353 (1992)CrossRef Chen, J., Solomon, R., Chan, T.Y., Ko, P.K., Hu, C.: Threshold voltage and C–V characteristics of SOI MOSFET’s related to Si film thickness variation on SIMOX wafers. IEEE Trans. Electron Devices 39, 2346–2353 (1992)CrossRef
14.
Zurück zum Zitat Bernstein, K., Norman, J.: SOI Circuit Design Concepts. Kluwer, Dordrecht (2000) Bernstein, K., Norman, J.: SOI Circuit Design Concepts. Kluwer, Dordrecht (2000)
15.
Zurück zum Zitat Kim, S.W., Choi, W.Y., Sun, M.-C., Park, B.-G.: Investigation on the corner effect of L-shaped tunneling field-effect transistors and their fabrication method. J. Nanosci. Nanotechnol. 13, 6376–6381 (2013)CrossRef Kim, S.W., Choi, W.Y., Sun, M.-C., Park, B.-G.: Investigation on the corner effect of L-shaped tunneling field-effect transistors and their fabrication method. J. Nanosci. Nanotechnol. 13, 6376–6381 (2013)CrossRef
16.
Zurück zum Zitat Lu, K., Dong, Y., Yang, W., Guo, Y.: Body effects on the tuning RF performance of PD SOI technology using four-port network. IEEE Electron Device Lett. 39, 795–798 (2018)CrossRef Lu, K., Dong, Y., Yang, W., Guo, Y.: Body effects on the tuning RF performance of PD SOI technology using four-port network. IEEE Electron Device Lett. 39, 795–798 (2018)CrossRef
17.
Zurück zum Zitat Kim, S.W., Choi, W.Y., Sun, M.-C., Kim, H.W., Park, B.-G.: Design guideline of Si-based L-shaped tunneling field-effect transistors. Jpn. J. Appl. Phys. 51, 06FE09 (2012)CrossRef Kim, S.W., Choi, W.Y., Sun, M.-C., Kim, H.W., Park, B.-G.: Design guideline of Si-based L-shaped tunneling field-effect transistors. Jpn. J. Appl. Phys. 51, 06FE09 (2012)CrossRef
18.
Zurück zum Zitat Fossum, G., Yang, J.-W., Trivedi, V.P.: Suppression of corner effects in triple-gate MOSFETs. IEEE Electron Device Lett. 24, 745 (2003)CrossRef Fossum, G., Yang, J.-W., Trivedi, V.P.: Suppression of corner effects in triple-gate MOSFETs. IEEE Electron Device Lett. 24, 745 (2003)CrossRef
19.
Zurück zum Zitat Goswami, R., Bhowmick, B.: Hetero-gate-dielectric gate-drain underlap nanoscale TFET with a δp + Si1–xGex layer at source-channel tunnel junction. Presented at CGCCEE 2014 International Conference on Green Computing Communication and Electrical Engineering, pp. 1–5 Goswami, R., Bhowmick, B.: Hetero-gate-dielectric gate-drain underlap nanoscale TFET with a δp + Si1–xGex layer at source-channel tunnel junction. Presented at CGCCEE 2014 International Conference on Green Computing Communication and Electrical Engineering, pp. 1–5
20.
Zurück zum Zitat Dash, S., Jena, B., Kumari, P., Mishra, G. P.: An analytical nanowire tunnel FET (NW-TFET) model with high-k dielectric to improve the electrostatic performance. Presented at PCITC 2015 IEEE Power, Communication and Information Technology Conference, pp. 447–451. Bhubaneswar (2015) Dash, S., Jena, B., Kumari, P., Mishra, G. P.: An analytical nanowire tunnel FET (NW-TFET) model with high-k dielectric to improve the electrostatic performance. Presented at PCITC 2015 IEEE Power, Communication and Information Technology Conference, pp. 447–451. Bhubaneswar (2015)
21.
Zurück zum Zitat Sentaurus Device User, Synopsys (2009) Sentaurus Device User, Synopsys (2009)
22.
Zurück zum Zitat Schenk, A.: Rigorous theory and simplified model of the band-to-band tunneling in silicon. Solid State Electron. 36, 19–34 (1993)CrossRef Schenk, A.: Rigorous theory and simplified model of the band-to-band tunneling in silicon. Solid State Electron. 36, 19–34 (1993)CrossRef
23.
Zurück zum Zitat Redwan, N.S., Chern, W., Hoyt, J.L., Antoniadis, D.A.: Trap assisted tunneling and its effect on subthreshold swing of tunnel FETs. IEEE Trans. Electron Devices 63, 4380–4387 (2016)CrossRef Redwan, N.S., Chern, W., Hoyt, J.L., Antoniadis, D.A.: Trap assisted tunneling and its effect on subthreshold swing of tunnel FETs. IEEE Trans. Electron Devices 63, 4380–4387 (2016)CrossRef
24.
Zurück zum Zitat Nguyen, B.-Y., Celler, G., Mazuré, C.: A review of SOI technology and its applications. J. Integr. Circuits Syst. 4, 51–54 (2009) Nguyen, B.-Y., Celler, G., Mazuré, C.: A review of SOI technology and its applications. J. Integr. Circuits Syst. 4, 51–54 (2009)
25.
Zurück zum Zitat Biswas, A., Dan, S.S., Royer, C.L., Grabinski, W., Ionescu, A.M.: TCAD simulation of SOI TFETs and calibration of non-local band-to-band tunneling model. Micro Electron. Eng. 98, 334–337 (2012)CrossRef Biswas, A., Dan, S.S., Royer, C.L., Grabinski, W., Ionescu, A.M.: TCAD simulation of SOI TFETs and calibration of non-local band-to-band tunneling model. Micro Electron. Eng. 98, 334–337 (2012)CrossRef
26.
Zurück zum Zitat Tsuchiya, T., Sato, Y., Tomizawa, M.: Three mechanisms determining short-channel effects in fully-depleted SOI MOSFETs. IEEE Trans. Electron Devices 45, 1116–1121 (1998)CrossRef Tsuchiya, T., Sato, Y., Tomizawa, M.: Three mechanisms determining short-channel effects in fully-depleted SOI MOSFETs. IEEE Trans. Electron Devices 45, 1116–1121 (1998)CrossRef
27.
Zurück zum Zitat Narang, R., Saxena, M., Gupta, R.S., Gupta, M.: Impact of temperature variations on the device and circuit performance of tunnel FET: a simulation study. IEEE Trans. Nanotechnol. 12, 951–957 (2013)CrossRef Narang, R., Saxena, M., Gupta, R.S., Gupta, M.: Impact of temperature variations on the device and circuit performance of tunnel FET: a simulation study. IEEE Trans. Nanotechnol. 12, 951–957 (2013)CrossRef
28.
Zurück zum Zitat Ehteshamuddin, M., Alharbi, A.G., Loan, S.A.: Impact of interface traps on the BTBT-current in tunnel field effect transistors. Presented at 2018 5th International Conference on Electrical and Electronics Engineering, pp. 224–227 (2018) Ehteshamuddin, M., Alharbi, A.G., Loan, S.A.: Impact of interface traps on the BTBT-current in tunnel field effect transistors. Presented at 2018 5th International Conference on Electrical and Electronics Engineering, pp. 224–227 (2018)
29.
Zurück zum Zitat Sharma, D., Vishvakarma, S.K.: Analyses of DC and analog/RF performances for short channel quadruple-gate gate-all-around MOSFET. Microelectron. J. 46, 731–739 (2015)CrossRef Sharma, D., Vishvakarma, S.K.: Analyses of DC and analog/RF performances for short channel quadruple-gate gate-all-around MOSFET. Microelectron. J. 46, 731–739 (2015)CrossRef
30.
Zurück zum Zitat Mohapatra, S.K., Pradhan, K.P., Artola, L., Sahu, P.K.: Estimation of analog/RF figures-of-merit using device design engineering in gate stack double gate MOSFET. Mater. Sci. Semicond. Process. 31, 455–462 (2015)CrossRef Mohapatra, S.K., Pradhan, K.P., Artola, L., Sahu, P.K.: Estimation of analog/RF figures-of-merit using device design engineering in gate stack double gate MOSFET. Mater. Sci. Semicond. Process. 31, 455–462 (2015)CrossRef
32.
Zurück zum Zitat Kranti, A., Armstrong, G.A.: Nonclassical channel design in MOSFETs for improving OTA gain-bandwidth trade-off. IEEE Trans. Circuits Syst. I Regul. Pap. 57, 3048–3054 (2010)MathSciNetCrossRef Kranti, A., Armstrong, G.A.: Nonclassical channel design in MOSFETs for improving OTA gain-bandwidth trade-off. IEEE Trans. Circuits Syst. I Regul. Pap. 57, 3048–3054 (2010)MathSciNetCrossRef
33.
Zurück zum Zitat Gautam, R., Saxena, M., Gupta, R.S., Gupta, M.: Effect of localised charges on nanoscale cylindrical surrounding gate MOSFET: analog performance and linearity analysis. Microelectron. Reliab. 52, 989–994 (2012)CrossRef Gautam, R., Saxena, M., Gupta, R.S., Gupta, M.: Effect of localised charges on nanoscale cylindrical surrounding gate MOSFET: analog performance and linearity analysis. Microelectron. Reliab. 52, 989–994 (2012)CrossRef
34.
Zurück zum Zitat Rawat, A.S., Gupta, S.K.: Potential modeling and performance analysis of junction-less quadruple gate MOSFETs for analog and RF applications. Microelectron. J. 66, 89–102 (2017)CrossRef Rawat, A.S., Gupta, S.K.: Potential modeling and performance analysis of junction-less quadruple gate MOSFETs for analog and RF applications. Microelectron. J. 66, 89–102 (2017)CrossRef
35.
Zurück zum Zitat Madan, J., Chaujar, R.: Interfacial charge analysis of heterogeneous gate dielectric-gate all around-tunnel FET for improved device reliability. IEEE Trans. Device Mater. Reliab. 16, 227–234 (2016)CrossRef Madan, J., Chaujar, R.: Interfacial charge analysis of heterogeneous gate dielectric-gate all around-tunnel FET for improved device reliability. IEEE Trans. Device Mater. Reliab. 16, 227–234 (2016)CrossRef
36.
Zurück zum Zitat Kumar, S.P., Agrawal, A., Chaujar, R., Gupta, R.S., Gupta, M.: Device linearity and intermodulation distortion comparison of dual material gate and conventional AlGaN/GaN high electron mobility transistor. Microelectron. Reliab. 51, 587–596 (2011)CrossRef Kumar, S.P., Agrawal, A., Chaujar, R., Gupta, R.S., Gupta, M.: Device linearity and intermodulation distortion comparison of dual material gate and conventional AlGaN/GaN high electron mobility transistor. Microelectron. Reliab. 51, 587–596 (2011)CrossRef
Metadaten
Titel
Reduction of the kink effect in a SELBOX tunnel FET and its RF/analog performance
verfasst von
Puja Ghosh
Brinda Bhowmick
Publikationsdatum
25.07.2019
Verlag
Springer US
Erschienen in
Journal of Computational Electronics / Ausgabe 4/2019
Print ISSN: 1569-8025
Elektronische ISSN: 1572-8137
DOI
https://doi.org/10.1007/s10825-019-01382-8

Weitere Artikel der Ausgabe 4/2019

Journal of Computational Electronics 4/2019 Zur Ausgabe

Neuer Inhalt