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2015 | OriginalPaper | Buchkapitel

1. Research and Development History of Three-Dimensional Integration Technology

verfasst von : Morihiro Kada

Erschienen in: Three-Dimensional Integration of Semiconductors

Verlag: Springer International Publishing

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Abstract

The first chapter of the book introduces research and development history of three-dimensional (3D) integration technology. Concept of through-Si via (TSV) is old but the industrialization of 3D integration technology was leaded by 3D packaging technology first. 3D integration technology development using TSV have been conducted word wide since around 2000. This chapter describes the 3D technology development history from the beginning through 2012.

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Nächstes Kapitel Recent Research and Development Activities of Three-Dimensional Integration Technology

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Garrou P (2007) Perspectives from the leading edge. The SIA meeting in NYC, mid Sept

Kada M (2005) Presentation slide toward the 3D-SiP era. SEMICON Japan

Kada M (2012) Presentation slide 3D-integrated circuits technologies—the history and future. ISSM Tokyo

Kada M (1999) Stacked CSP/a solution for system LSI. Chip Scale International Technical Symposium Semicon West, B1-B7, Sept13

Kada M, Smith L (2000) Advancements in Stacked Chip Scale Packaging (S-CSP), provides system-in-a-package functionality for wireless and handheld applications. Pan Pacific Microelectronics Symposium Conference, Jan. http://www.eet.bme.hu/~benedek/CAD_Methodology/Courses/packaging/PanPacific_StackedCSP_RevG1.pdf. Accessed 9 July 2014

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10.

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11.

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13.

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14.

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15.

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16.

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17.

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18.

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19.

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20.

NEDO Assessment Committee (2008) Stacked memory chip technology development project report of after project. Assessment Feb (in Japanese). http://www.nedo.go.jp/content/100096542.pdf. Accessed 25 June 2014

21.

Kada M (2009) Development on functionally innovative 3D-integrated circuit (dream chip) technology. 3D system integration conference

22.

Kada M (2009) Highly performance TSV is pursued towards “dream chip”, simulator, peripheral technology, such as proving technology, are also developed. The semiconductor technology yearbook, Nikkei BP (in Japanese)

23.

ASET (2009) R&D result of “dream chip project” ASET annual symposium 2010 (in Japanese)

24.

NEDO R&D Assessment Committee (2010) Dream chip development project, report of interim project assessment, Nov (in Japanese). http://www.nedo.go.jp/content/100140983.pdf. Accessed 25 June 2014

25.

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26.

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27.

Home Page Research Center for Three Dimensional Semiconductors (2014) (in Japanese). http://www.tl.fukuoka-u.ac.jp/~tomokage/3dcenter/toppage.html. Accessed 22 April 2014

28.

ASET (2013) Presentation slide dream-chip project by ASET (final result). March 8, http://aset.la.coocan.jp/english/e-kenkyu/Dream_Chip_Pj_Final-Results_ASET.pdf. Accessed 12 July 2014

29.

Fritze M et al (2007) Presentation slide thermal challenges in DARPA’s 3DIC Portfolio, Sematech workshop on “Thermal & Design Issues in 3D IC’s” Albany, NY, Oct 11–12. http://www.sematech.org/meetings/archives/3d/8334/pres/Fritze-Steer.pdf. Accessed 19 July 2014

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31.

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Keast C et al (2009) Presentation slide A SOI-based wafer-scale 3-D circuit integration technology. 3D architectures for semiconductor integration and packaging, Dec 11

33.

Sematech (2004) Press release international SEMATECH identifies top technical challenges for 2005. http://www.sematech.org/corporate/news/releases/20040610a.htm. Accessed 17 April 2014

34.

Sematech (2006) Press release SEMATECH launches 3D project to probe options for advanced interconnect. http://www.sematech.org/corporate/news/releases/20060209htm. Accessed 17 April 2014

35.

Sematech (2010) Press release new 3D enablement program launched by SEMATECH, SIA and SRC. http://www.azonano.com/news.aspx?newsID=20908. Accessed 17 April 2014

36.

Arkalgud S (2011) Presentation slide 3D interconnects 3D enablement center. Annual SEMATECH symposium Hsinchu, Sept 13. http://www.sematech.org/meetings/archives/symposia/10187/Session2/01Arkalgudl.pdf. Accessed 11 July 2014

37.

Ramm P et al (2010) Presentation slide, welcome to the IEEE international 3D system integration conference (3DIC). Munich, Nov 16–18

38.

Ramm P et al (2010) The European 3D technology platform (e-CUBES). IMAPS, http://www.sintef-norge.com/upload/IKT/9031/Ramm%20IMAPS%20Device%20Packaging%202010.pdf. Accessed 13 July 2014

39.

Lietaer N et al (2009) Presentation slide 3D integration technologies for miniaturized tire pressure monitor system (TPMS). Lietaer09—IMAPS symposium Foredrage, http://sintef.org/upload/IKT/9031/Lietaer09%20-%20IMAPS%20Symposium%202009%20Foredrag.pdf. Accessed 25 June 2014

40.

Ramm P et al (2013) Presentation slide the e-BRAINS project. ESSDERC/ESSCIRC, Bucharest Romania workshop: In the quest for zero power: enabling smart autonomous system applications. http://www.e-brains.org/data/events/uploads/Peter_Ramm_The_e-BRAINS_Project_ESSDERC_2013_WS_In_The_Quest_For_Zero_Power.pdf. Accessed 13 July 2014

41.

http://www.e-brains.org/project/rtd/. Accessed 26 April 2014

42.

IMEC (2005) Press release IMEC packaging research center attracts 30 companies. www.embedded.com/print/4054184. Accessed 2 March 2014

43.

IMEC (2008) Brochure 3D @ IMEC, http://www2.imec.be/content/user/File/3D_brochure.pdf. Accessed 13 July 2014

44.

Qualcomm (2008) Press release Qualcomm and IMEC collaborate on 3D integration research. http://www.cn-c114.net/577/a330029.html. Accessed 2 March 2014

45.

IMEC (2011) Press release IMEC extends 3D research agreement with Qualcomm focusing on advanced technologies and devices. http://www2.imec.be/be_en/press/imec-news/imecqualcomminsite.html. Accessed 2 March 2014

46.

TSMC and IMEC (2009) Press release TSMC and IMEC join forces to bring novel technology solutions to emerging markets. http://www.leuveninc.com/event/36/784/TSMC_and_IMEC_join_forces_to_bring_novel_technology_solutions_to_emergin/. Accessed March 2, 2014

47.

Beyne E (2011) Presentation slide 3D system integration technology convergence. Semicon Europe, Messe Dresden, Germany, Oct 10–13, http://semieurope.omnibooksonline.com/2011/semicon_europa/SEMI_TechARENA_presentations/3DICsession_02_Eric.Beyne_IMEC.pdf. Accessed 14 July 2014

48.

CEA Leti (2011) Press release CEA-Leti Ramps up 300 mm line dedicated to 3D-integration applications. Accessed 18 Apr 2014

49.

CEA Leti (2012) Press release CEA-Leti launches open 3D™ initiative. Accessed 18 April 2014

50.

Ad-stac HP, http://ad-stac.itri.org.tw/memb/index_e.aspx. Accessed 26 April 2014

51.

Tsai MJ (2011) Presentation slide overview of ITRI’s TSV Technology, 2011-06-22, http://www.sematech.org/meetings/archives/symposia/9237/Session%205%203D%20interconnect/1%20MJ_Tsai_ITRI.pdf. Accessed 9 July 2014

52.

Kim G (2009) Presentation slide TSV based 3D technologies in Korea. TSV technology conference, NIKKEI MICRODEVICES, 2009-04-16

53.

A*STAR (2011) Press release A *STAR Institute of Microelectronics and Tezzaron Team Up to Develop 2.5D3D through-silicon interposer technology. http://www.bizwireexpress.com/showstoryACN.php?storyid=26505538. Accessed 26 April 2014

54.

A*STAR (2012) Press release A-STAR institute of microelectronics and UMC to develop TSV technology for BSl image sensor used in mobile applications. http://www.advfn.com/news_A-STAR-Institute-of-Microelectronics-and-UMC-to-De_52659319.html. Accessed 26 April 2014

55.

A*STAR (2012) Press release A*STAT of microelectronics and Huawei announced joint effort to develop 25D/3D through-silicon interposer technology. https://www.astar.edu.sg/Portals/30/news/IMEFuturewei%20Press%20Release%20Final.pdf. Accessed 26 April 2014

56.

Siblerud P, Kim B (2007) Presentation slide EMC-3D consortium overview and COC Model”. Jan 22–26, http://atlas-old.lal.in2p3.fr/elec/EMC3DEu/documents/Semitool-Consortium%20Overview.pdf. Accessed 18 July 2014

57.

3DASMM Consortium (2008) News release new consortium formed focusing on Si interposer technologies. http://www.i-micronews.com/news/3D-consortiumof-formed-focusing-Si-interposer-technologies,1464.html. Accessed 26 April 2014

58.

Toshiba (2007) Press release strengthening of CMOS image sensor business by in-house production of COMS camera module for mobile phone. (in Japanese), http://www.toshiba.co.jp/about/press/2007_10/pr_j0102.htm. Accessed 26 April 2014

59.

Micron (2008) News release micron introduces wafer level camera technology with TSV interconnects. http://www.i-micronews.com/news/Micron-wafer-level-camera-TSV-interconnects,1025.html. Accessed 26 April 2014

60.

ST Micro (2011) Press release ST microelectronics first to use through-silicon vias for smaller and smarter MEMS chips. http://www.bizjournals.com/prnewswire/press_releases/2011/10/11/NY84151. Accessed 26 April 2014

61.

Elpida (2011) Press release Elpida to start to ship sample of 8 Gbit DDR3 SDRAM of X32 using TSV. (in Japanese). http://techon.nikkeibp.co.jp/article/NEWS/20110627/192909/. Accessed 27 April 2014

62.

Samsung (2011) Press release Samsung develops 30 nm-class 32 GB green DDR3 for next-generation servers using TSV package technology. http://www.samsung.com/global/business/semiconductor/news-events/press-releases/detail?newsId=4014. Accessed 27 April 2014

63.

Hynix (2011) Press release Hynix semiconductor joins SEMATECH 3D interconnect program at UAibany Nano College. http://electroiq.com/blog/2011/03/hynix-semiconductor/. Accessed 27 April 2014

64.

JEDEC (2012) Press release JEDEC publishes breakthrough standard for wide I/O mobile DRAM. http://www.jedec.org/news/pressreleases/jedec-publishes-breakthrough-standard-wide-io-mobile-dram. Accessed 27 April 2014

65.

JEDEC (2011) STANDAD JESD229 wide I/O single data rate (Wide I/O SDR) wide I/O single data rate. December

66.

Samsung and Micron (2011) Press release micron and samsung launch consortium to break down the memory wall. http://investors.micron.com/releasedetail.cfm?releaseid=611879. Oct 6, Accessed 3 July 2014

67.

IBM and Micron (2011) Press release IBM to produce Micron’s hybrid memory cube in debut of first commercial, 3D chip-making capability. IBM news room. https://www-03.ibm.com/press/us/en/pressrelease/36125.wss. Accessed 15 Aug 2014

68.

HMCC (2012) Press release microsoft joins hybrid memory cube consortium. http://investors.micron.com/releasedetail.cfm?releaseid=671388. Accessed 3 July 2014 (May 8)

69.

HMCC (2012) Press release consortium to accelerate dramatic advances in memory technology announces new members. http://investors.micron.com/releasedetail.cfm?ReleaseID=686974. Accessed 3 July 2014 (June 27)

70.

HMCC (2012) Press release first draft of hybrid memory cube interface specification released. http://news.micron.com/releasedetail.cfm?ReleaseID=700331. Accessed 3 July 2014 (August 14)

71.

Xilinx (2010) Press release Xllinx stacked silicon interconnect extends FPGA technology to deliver ‘More than Moore’ density, bandwidth and power efficiency. http://press.xilinx.com/2010–10-26-Xilinx-Stacked-Silicon-Interconnect-Extends-FPGA-Technology-to-Deliver-More-than-Moore-Density-Bandwidth-and-Power-Efficiency. Accessed 27 April 2014

72.

Xilinx (2012) White paper: Virtex-7 FPGAs, Xilinx stacked silicon interconnect technology delivers breakthrough FPGA capacity, bandwidth, and power efficiency Virtex-7 FPGAs. http://www.xilinx.com/support/documentation/white_papers/wp380_Stacked_Silicon_Interconnect_Technology.pdf. Accessed 11 July 2014 (December 11)

73.

Xilinx (2011) Press release Xllinx ships world’s highest capacity FPGA and shatters industry record for number of transistors by 2X. http://press.xilinx.com/2011–10-25-Xilinx-Ships-Worlds-Highest-Capacity-FPGA-and-Shatters-Industry-Record-for-Number-of-Transistors-by-2X. Accessed 27 April 2014

74.

TSMC and Altera (2010) Press release TSMC, Altera team on 3-D IC test vehicle. http://www.eetimes.com/document.asp?doc_id=1261410. Accessed 12 June 2014

75.

Knickerbocker JU (2012) IBM presentation slide 3D integration & packaging challenges with through-silicon-vias (TSV). USA NSF Workshop—2/02/2012, http://weti.cs.ohiou.edu/john_weti.pdf. Accessed 3 July 2014

76.

I-Micronews (2012) Qualcomm integrates Wide IO Memory onto 28 nm logic chip. http://www.i-micronews.com/news/Qualcomm-integrates-Wide-IO-Memory-onto-28-nm-logic-chip,9605.html. Accessed 27 April 2014 (Oct 3)

77.

TechFreep (2006) Hardware news Intel’s TSV connects processors to memory. http://techfreep.com/intels-tsv-connects-processors-to-memory.htm. Accessed 27 April 2014 (Sept 28)

78.

EETimes (2010) India news 3D TSV chips still pre-mature. http://www.eetindia.co.in/ART_8800610003_1800007_NT_192ccb4b.HTM. Accessed 6 Aug 2011 (18 Jun)

Titel: Research and Development History of Three-Dimensional Integration Technology
verfasst von: Morihiro Kada
Verlag: Springer International Publishing
Buch: Three-Dimensional Integration of Semiconductors
Print ISBN: 978-3-319-18674-0

Electronic ISBN: 978-3-319-18675-7

Copyright-Jahr: 2015
DOI: https://doi.org/10.1007/978-3-319-18675-7_1

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