Research on Verification Method of PCIe IP Core Based on Programmable Logic

With the development of nuclear power digital instrument control technology, IP core, as an indispensable part of FPGA chips, is more and more involved in the realization of important functions of instrument control products. Due to the high reliability requirements in the nuclear power field, it is necessary to fully verify the logical functions of IP cores. Traditional verification methods cannot meet the requirements of complex IP core verification quality and efficiency due to the use of directional testing and poor reusability. This paper proposes a method based on UVM construction of IP core verification platform, through the analysis of IP core application scenarios, and uses UVM components to realize the hierarchy and reusability, and finally, random test excitation generated by components is injected into the tested IP through the verification module, and the output data is monitored to check whether it is consistent with the expected value. This method can quickly build a verification platform, and the random excitation generated by the platform can fully verify IP. The paper takes the PCIe X4 IP verification of domestic FPGA as an example to explain how to use this method to build a verification platform and execute test cases. By practice, this method shortens the verification time and improves the verification efficiency.