RF and linearity parameters analysis of 20 nm gate-all-around gate-stacked junction-less accumulation mode MOSFET for low power circuit applications

For low-power circuit applications, the performance of the circuit is significantly influenced by the MOSFET's analog/RF and non-linearity properties. Gate-all-around junction-less accumulation mode MOSFETs (JAM) are now the perfect choice for low-power circuit applications. In the present work, the gate-stack engineering method is used for gate-all-around junction-less accumulation mode MOSFET (GSJAM) to improve the analog/RF characteristics. The analog/RF and linearity parameter analyses are numerically performed for a 20 nm channel length gate-all-around gate-stacked junction-less MOSFET using an ATLAS 3D device simulator. The comparative analysis of these analog/RF and linearity parameters is also done. The gate stack engineering shows significant improvements in analog/RF parameters, i.e., trans-conductance (g_m), output resistance (R_out), early voltage (V_ea), intrinsic gain (A_V), trans-conductance frequency product (TFP), gain frequency product (GFP), trans-conductance generation factor (TGF), gain bandwidth product (GBWP), gain trans-conductance frequency product (GTFP), and cut-off frequency (f_T). The results of the simulation investigation show that when GSJM is compared to JAM MOSFET, the values of gm, R_out, V_ea, and TGF are all 26.37%, 2.24 times, 22.38%, and 20.78% higher, respectively. Also, the gate-stack junction-less MOSFET improves the linearity parameters, i.e., 2nd -order trans-conductance (g_m2)_, 3rd -order trans-conductance (g_m3), VIP₂, VIP₃, IIP₃, IMD₃, and 1-dBCP. When comparing GSJAM to JAM MOSFET, the values of VIP2 are 81.63% higher, VIP3 is 1.77 times higher, IIP3 is 6.72 times higher, and 1-dBCP is twice as high. Further, for analog/RF applications, a 20 nm CMOS common-source voltage amplifier circuit using gate-stake junction-less MOSFET has also been designed for a 20 mV and 1 GHz sinusoidal input signal.