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2020 | OriginalPaper | Buchkapitel

RiCaSi: Rigorous Cache Side Channel Mitigation via Selective Circuit Compilation

verfasst von : Heiko Mantel, Lukas Scheidel, Thomas Schneider, Alexandra Weber, Christian Weinert, Tim Weißmantel

Erschienen in: Cryptology and Network Security

Verlag: Springer International Publishing

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Abstract

Cache side channels constitute a persistent threat to crypto implementations. In particular, block ciphers are prone to attacks when implemented with a simple lookup-table approach. Implementing crypto as software evaluations of circuits avoids this threat but is very costly.
We propose an approach that combines program analysis and circuit compilation to support the selective hardening of regular C implementations against cache side channels. We implement this approach in our toolchain RiCaSi. RiCaSi avoids unnecessary complexity and overhead if it can derive sufficiently strong security guarantees for the original implementation. If necessary, RiCaSi produces a circuit-based, hardened implementation. For this, it leverages established circuit-compilation technology from the area of secure computation. A final program analysis step ensures that the hardening is, indeed, effective.

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Vorheriges Kapitel Integral Cryptanalysis of Reduced-Round Tweakable TWINE
Nächstes Kapitel Assembly or Optimized C for Lightweight Cryptography on RISC-V?
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Metadaten
Titel
RiCaSi: Rigorous Cache Side Channel Mitigation via Selective Circuit Compilation
verfasst von
Heiko Mantel
Lukas Scheidel
Thomas Schneider
Alexandra Weber
Christian Weinert
Tim Weißmantel
Copyright-Jahr
2020
Buch
Cryptology and Network Security

Print ISBN: 978-3-030-65410-8

Electronic ISBN: 978-3-030-65411-5

Copyright-Jahr: 2020

DOI
https://doi.org/10.1007/978-3-030-65411-5_25

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