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Journal of Computational Electronics
Erschienen in: Journal of Computational Electronics 3/2016

21.05.2016

Role of annealing temperature in the oxide charge distribution in high-\(\kappa \)-based MOS devices: simulation and experiment

verfasst von: Debaleen Biswas, Ayan Chakraborty, Supratic Chakraborty

Erschienen in: Journal of Computational Electronics | Ausgabe 3/2016

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Abstract

The effect of rapid thermal annealing on the oxide charge distribution of Al/HfO\(_2\)/SiO\(_2\)/Si metal–oxide–semiconductor structures are studied using technology computer-aided design (TCAD) simulations and experiments. The simulated electrical characteristics are compared with experimentally obtained data. The interface traps are found to be nonuniform in nature and laterally distributed following a Gaussian profile. The distribution of interface trap charges arises because of spatial electric field variation in the oxide film upon gate bias application. The interface trap density is found to decrease with increase in annealing temperature. It is further observed that, at higher annealing temperature, the fixed oxide charge density increases due to interfacial Hf silicate formation.
Vorheriger Artikel Uncoupled mode space approach for analysis of nanoscale strained junctionless double-gate MOSFET
Nächster Artikel Optimization of saddle junctionless FETs for extreme high integration

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Metadaten
Titel
Role of annealing temperature in the oxide charge distribution in high--based MOS devices: simulation and experiment
verfasst von
Debaleen Biswas
Ayan Chakraborty
Supratic Chakraborty
Publikationsdatum
21.05.2016
Verlag
Springer US
Erschienen in
Journal of Computational Electronics / Ausgabe 3/2016
Print ISSN: 1569-8025
Elektronische ISSN: 1572-8137
DOI
https://doi.org/10.1007/s10825-016-0829-y

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