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Journal of Electronic Testing
Erschienen in: Journal of Electronic Testing 5/2019

19.11.2019

SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement

verfasst von: Binod Kumar, Masahiro Fujita, Virendra Singh

Erschienen in: Journal of Electronic Testing | Ausgabe 5/2019

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Abstract

Silicon debugging of integrated circuits is exacerbated by the lack of golden responses, highly restricted observability and irreproducible nature of bugs. Debug engineers need to develop better methods that can assist in error localization at lower level(netlist) granularity. It is widely accepted that root-cause analysis of electrical bugs is highly difficult which further elongates the time needed to fix them. This paper revisits methodologies to debug electrical errors through satisfiability(SAT) solving under a limited visibility environment. We propose various SAT formulations and analyze their efficacy in error localization for a variety of benchmark circuits. The selection of debugging instrumentation is an important issue in post-silicon validation. We analyze different graph-based signal tracing techniques and propose a methodology that utilizes clustering of the nodes of the circuit graph. We aim at minimizing the overhead associated with signal tracing while maintaining the error localization efficacy. We address scalability concerns in SAT solving through partitioning of large error traces. We provide localization results on two different error models (bit-flip and stuck-at) and evaluate its efficiency through a set of different metrics.
Vorheriger Artikel Classical Cryptanalysis Attacks on Logic Locking Techniques
Nächster Artikel Equivalence Checking and Compaction of n-input Majority Terms Using Implicants of Majority

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Fußnoten
1
In the previous version of this work [28], a preliminary signal grouping methodology was proposed. The experimental evaluation was limited to only a few circuits and iterated over them only for 10 times. The experiments have been redesigned in this version and are elaborately presented in Section 5. The detailed experiments assist in capturing the essence of different SAT formulations.
 
2
This notion of signal state restoration is totally different from the widely used terminology of state restoration in the field of processor designs/computer architecture.
 
3
This is slightly different from the notion of scan chains widely utilized in manufacturing testing. In this context, the input to the chain comes from the circuit components and the output is fed to the trace buffer. The dumping of contents as illustrated in Table 2 shows the connection of the signals in the chain and the resulting dumping frequency.
 
4
the notion of stuck-at here refers to electrical error manifestations because of different reasons. This does not essentially refer to the stuck-at fault of manufacturing testing
 
5
We are assuming a TBw of 2 which equals Nclu.
 
6
Since signals corresponding to the techniques of [25] and [15] are not available publicly, we implemented these procedures and obtained those signals after the analysis of Gdir for different benchmarks utilized in our experiments.
 
7
It is clear that j can take the values of 1,2,3 or 4.
 
8
In the previous version of this work([28]), the evaluation of efficacy was done only in terms of size of Sufc. That evaluation becomes clearly an over-simplified quantification of the methodology and did not consider inexact localization.
 
9
This method of obtaining a topological order for cyclic graphs is similar to the methodology presented in [22].
 
10
Another way of evaluation could be dividing the numerator of metrics ϕ3, ϕ4 and ϕ7 by ϕ1 instead of NE.
 
11
The reported numbers on Y-axis denote the wall clock time (elapsed time) taken by a command to get executed.
 
12
Based on the reported results in the respective works. For the proposed approach, the temporal and spatial localization numbers reported have been obtained by averaging the results of s38417 and s38584 circuits.
 
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Metadaten
Titel
SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement
verfasst von
Binod Kumar
Masahiro Fujita
Virendra Singh
Publikationsdatum
19.11.2019
Verlag
Springer US
Erschienen in
Journal of Electronic Testing / Ausgabe 5/2019
Print ISSN: 0923-8174
Elektronische ISSN: 1573-0727
DOI
https://doi.org/10.1007/s10836-019-05830-y

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