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Journal of Cryptographic Engineering

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01.09.2015 | Regular Paper

Security analysis of concurrent error detection against differential fault analysis

verfasst von: Xiaofei Guo, Debdeep Mukhopadhyay, Chenglu Jin, Ramesh Karri

Erschienen in: Journal of Cryptographic Engineering | Ausgabe 3/2015

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Abstract

Differential fault analysis (DFA) poses a significant threat to advanced encryption standard (AES). Only a single faulty ciphertext is required to extract the secret key. Concurrent error detection (CED) is widely used to protect AES against DFA. Traditionally, these CEDs are evaluated with uniformly distributed faults, the resulting fault coverage indicates the security of CEDs against DFA. However, DFA-exploitable faults, which are a small subspace of the entire fault space, are not uniformly distributed. Therefore, fault coverage does not accurately measure the security of the CEDs against DFA. We provide a systematic study of DFA of AES and show that an attacker can inject biased faults to improve the success rate of the attacks. We propose fault entropy (FE) and fault differential entropy (FDE) to evaluate CEDs. We show that most CEDs with high fault coverage are not secure when evaluated with FE and FDE. This work challenges the traditional use of fault coverage for uniformly distributed faults as a metric for evaluating the security of CEDs against DFA.

Nächster Artikel Vertical and horizontal correlation attacks on RNS-based exponentiations

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Appendix A describes the AES encryption algorithm.

Classic fault model, such as permanent single bit stuck-at faults, is not relevant for DFA.

Single, stuck-at fault model. The assumption of random fault in DFA is not relevant.

The number of faults is calculated with an assumption that the faults are injected at the input to the round. If the faults can be injected anywhere in the AES round, all these numbers can be proportionally scaled.

In practice, it may be subjected to clock, power, laser, or EM injection attack, but it is relatively feasible and affordable to use multiple countermeasures on the checker. To defend against clock glitch attack, one can use dual rail logic style [50]. To defend against power or EM pulse attack, one can use a power supply noise detector for the checker [40]. To defend against laser, one can use shielding [16].

This is demonstrated using clock glitch in Dutertre et al. [21].

This is demonstrated using laser in Canivet et al. [13].

For more details, we refer to [19].

The evaluation is similar to the attack presented in Lashermes et al. [34].

\(i\) and \(j\) are the row and column indices of the state matrix, respectively. Appendix 7.1 contains the detail of the AES algorithm.

The details of SubBytes are in Appendix A.

This means eight bit binary value in hex.

We compute the difference between the fault-free and the faulty 10th round input.

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Titel: Security analysis of concurrent error detection against differential fault analysis
verfasst von: Xiaofei Guo
Debdeep Mukhopadhyay
Chenglu Jin
Ramesh Karri
Publikationsdatum: 01.09.2015
Verlag: Springer Berlin Heidelberg
Erschienen in: Journal of Cryptographic Engineering / Ausgabe 3/2015
Print ISSN: 2190-8508
Elektronische ISSN: 2190-8516
DOI: https://doi.org/10.1007/s13389-014-0092-8

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