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Über dieses Buch

This book covers various aspects of security, privacy and reliability in Internet of Things (IoT) and Cyber-Physical System design, analysis and testing. In particular, various established theories and practices both from academia and industry are presented and suitably organized targeting students, engineers and researchers. Fifteen leading academicians and practitioners wrote this book, pointing to the open problems and biggest challenges on which research in the near future will be focused.



Security and Trust Verification of IoT SoCs

System-on-Chips (SoCs) are widely used in designing Internet-of-Things (IoT) devices. In order to ensure the security of IoT devices, it is crucial to guarantee the trustworthiness of SoCs. Verifying the trust in SoCs is a major challenge due to their long and globally distributed supply chain. Malicious components can be inserted in different stages of the design cycle. These malicious functionalities work as a backdoor to severely affect the security of the design by giving control of the system to adversaries. The threat creates a critical need for designing new validation approaches that are capable of identifying hidden Trojans. Existing validation techniques cannot efficiently activate and detect Trojans since Trojans are designed to be inactive most of the time and triggered using very rare events. For example, if an adversary wants to hide a Trojan in register-transfer level (RTL) designs, rare branches would be an ideal choice to host Trojans. In this chapter, we introduce a Trojan activation technique that utilizes an effective combination of symbolic simulation as well as concrete execution to identify Trojans that are hidden under rare branches and assignments. The technique is scalable as it considers one path at a time instead of considering the whole design. It uses satisfiability modulo theories (SMT) solvers to solve the path constraints in order to generate a valid test to explore a new path in the design. The exploration continues until all of the rare branches in the design are activated in the search for hidden Trojans.
Alif Ahmed, Farimah Farahmandi, Yousef Iskander, Prabhat Mishra

Low Cost Dual-Phase Watermark for Protecting CE Devices in IoT Framework

Intellectual property (IP) core providers are increasingly aware of the need to protect their investment from either counterfeit/forgery or illegal ownership. This chapter presents a novel low cost dual phase watermarking methodology during high level synthesis (HLS) for IP core protection of vendor. Robust vendor signature is embedded in two subsequent phases of high level synthesis to form an integrated watermark. We present a dual-phase watermarking methodology that embeds a multi-variable double phase watermarking during high level synthesis for application specific IPs (application specific integrated circuits) that incurs zero delay and register overhead as well as minimal hardware overhead. The dual-phase watermarking approach yields average reduction of embedding cost of 6% (which includes average area reduction of 7% and average latency reduction of 4%) when compared to two recent HLS based watermarking approaches for application specific IPs. Additionally, the approach also achieves stronger proof of authorship compared to two recent HLS based watermarking approaches.
Anirban Sengupta, Dipanjan Roy

Secure Multicast Communication Techniques for IoT

With the advent of Internet of Things (IoT) and the wide number of applications that it is being applied on, eventually it will surpass the present size of the Internet. But with these number of devices serving so many applications and being reachable remotely over the Internet, they become equally prone towards attacks and vulnerabilities. Hence, efficient and secure mechanisms tailored to such portable devices are to be designed. Most importantly the protocols running on these devices need to satisfy the basic security requirements while consuming minimum resources in terms of memory, bandwidth and power. Also as these devices will be in millions there is an increasing need to design multicast security mechanisms as many of the applications require it. Till date there has been limited contribution towards multicast security with approaches made mainly based on extending the DTLS protocol, which certainly has a number of drawbacks. In this chapter, we discuss major requirements of secure group communication and present different secure multicast communication techniques emphasizing an interesting and effective approach called S-CPABE.
Subho Shankar Basu, Somanath Tripathy

An Adaptable System-on-Chip Security Architecture for Internet of Things Applications

Modern-day System-on-Chip (SoC) security architectures designed for smart connected devices, such as Internet of Things (IoT) and automotive applications, are often confined by two crucial design aspects: in-field configuration and low overhead. Due to the restrictions posed by these design aspects, it is extremely difficult to develop a robust and adaptable architecture for SoC security policies in IoT and automotive platforms. Security policies, on the other hand, are of critical significance as they implement the confidentiality, integrity, and availability requirements of diverse on-chip security assets. During the complex and often a long life of a system, security requirements evolve, giving rise to the need of adapting security policies. Existing SoC architecture and design flow do not provide the flexibility for easy adaptation of SoC security policies based on emerging threats or security requirements. To address these design constraints and subsequent limitations, a novel security architecture and CAD flow is proposed in this work for efficient implementation of diverse security policies. The adaptable architecture and associated CAD flow enable hardware patching through a reconfigurable security policy engine that can be seamlessly and securely upgraded in-field to address unanticipated attacks and update new security requirements. The infrastructure of the proposed security framework is build with three primary building blocks. First, a centralized Reconfigurable Security Policy Engine (RSPE) is introduced to implement and upgrade policies in-field without comprehensive changes in the architecture. Second, a set of smart security wrappers are developed for efficient extraction of security critical event information and avoidance of communication bottleneck. Third, the on-chip debug instrumentation i.e.  the Design-for-Debug (DfD) infrastructure is employed with minimal modification for extensive access to an arbitrary number of signals of the SoC. A suitable CAD framework is also proposed along with the architecture to systematically implement diverse security policies. The result analysis shows that the architecture provides a high level of adaptability with minimal overhead in terms of power, area, energy, and performance. Hence, the security architecture is highly suited for SoC in IoTs and automotive systems operating in a rigid boundary of performance and energy profiles.
Atul Prasad Deb Nath, Tamzidul Hoque, Sandip Ray, Swarup Bhunia

Lightweight Fault Tolerance for Secure Aggregation of Homomorphic Data

Homomorphic encryption constitutes a powerful cryptographic method that enables data aggregation in distributed applications over large datasets, such as electronic voting, electronic wallets, secure auctions, lotteries and secret sharing. At the same time, as attack trends move towards the lower levels of the computation stack and new threats continue to emerge, the lack of trust in contemporary computing paradigms keeps increasing. Since, homomorphic encryption helps preserve the confidentiality of sensitive information, it offers a powerful countermeasure against contemporary and future privacy threats, while allowing meaningful processing even though the data remains unreadable. Nevertheless, when homomorphic primitives are mapped to hardware circuits to improve performance, they become vulnerable to random faults and soft errors since homomorphic operations are malleable by construction and do not provide any explicit assurance towards data integrity. In this chapter, we present a fault tolerance methodology that protects homomorphic aggregation circuits through concurrent detection of random errors in homomorphic ALUs and encrypted values stored in memory. Our approach establishes the theoretical foundations to extend residue numbering to additive homomorphic operations, which enables lightweight fault detection with detection rates of more than 99.98% for ALU operations, and 100% for clustered faults and single bitflips in memory values. Using an efficient modular reduction algorithm, our method incurs a performance overhead between 3.6 and 8%, for a minimal area penalty.
Nektarios Georgios Tsoutsos, Michail Maniatakos

An Approach to Integrating Security and Fault Tolerance Mechanisms into the Military IoT

Security and dependability are the most crucial challenges for the IoT implementation into the military domain. Insufficiently secured military IoT can provide adversary possibility of manipulation or disruption of data transmitted between units or even taking control of or disabling automated systems. On the other hand, if we already apply certain security mechanisms, IoT network should work reliably, even with faults arising out of unreliable hardware, and harsh or even hostile physical environment. In the paper it was pointed out that security mechanisms and fault-tolerant techniques to be effective in military applications should be tightly integrated. An approach for integrating security techniques on the access layer and the fault-tolerant techniques which are based on faulty (or misbehaving) sensor nodes diagnosis and reconfiguration was proposed. Presented solutions for securing the military IoT network ensure strong nodes authentication within network clusters and securing data transmissions between sensor nodes (SN) and gateways with the use of COTS IoT platforms equipped with TPM modules. Fault diagnosis (or detection) is based on the comparison method within network clusters. The method for determining effective diagnosable structures within clusters was presented. An experimentally constructed network called SFTN was build to demonstrate the proposed approach. Also, some results from a study of the experimental network in Cooja simulator were conducted.
Zbigniew Zieliski, Jan Chudzikiewicz, Janusz Furtak

Fault-Tolerant Implementations of Physically Unclonable Functions on FPGA

Most of the faults in circuits or systems occur due to the unintentional but natural phenomenon (e.g. imperfection in manufacturing process or significant change in the working environment), and thus, these faults are often follow a pattern and comparatively easier detect than the intentional faults. In the context of secure design/system, the adversary (intentionally) injects some faults in the system to bypass the security protection or reveal secret information. Since the adversaries’ fault injection objectives are often very subjective, it is difficult to find a pattern among the faults in a system, and this makes the fault detection and fault recovery difficult in a secure system. In this chapter, we discuss possible intentional faults in an emerging hardware security primitive, known as Physically Unclonable Functions (PUFs). We show how the faults vary over the PUF designs and its applications. In addition, we explain different fault detection circuits and fault recovery techniques which are specific to PUF designs and their implementations on FPGA platforms.
Durga Prasad Sahoo, Arnab Bag, Sikhar Patranabis, Debdeep Mukhopadhyay, Rajat Subhra Chakraborty

Fault Tolerance in 3D-ICs

The systems with emerging technologies like Internet-of-Things and beyond Von-Neumann architectures can be produced in large scale only if they are resilient-aware, cost-effective and secure. The resilient and cost-effective solutions can be achieved by incorporating fault tolerance techniques at the architecture level of the system design is one of the plausible solutions. The choice of various fault tolerance techniques gives the designers a freedom to incorporate these in the early stage of the design and in turn leading to high yield and reliable architectures. Through-silicon-via (TSV) interconnects based three-dimensional integrated circuits are emerging technologies consisting of vertical communication between the stacked dies, leading to the decrease of wire length and thus enhances the system performance. However, yield and reliability are the major issues that hinder resilient and cost-effective solutions for 3D-IC design. These can be addressed by incorporation of fault tolerance techniques.
Raviteja P. Reddy, Amit Acharyya, Saqib Khursheed

Formal Verification for Security in IoT Devices

Online detection of cyber-attacks on IoT devices is extremely difficult due to the limited battery and computational power available in these devices. An alternate approach is to shrink the attack surface in order to reduce the threat of attack. This would require that the device undergo more stringent security tests before deployment. Formal verification is a promising tool that can be used to not only detect potential vulnerabilities but also provide guarantees of security. This chapter reviews several security issues that plague IoT devices such as functional correctness of implementations, programming bugs, side-channel analysis, and hardware Trojans. In each of these cases, we discuss state-of-the-art mechanisms that use formal verification tools to detect the vulnerability much before the device is deployed.
K. Keerthi, Indrani Roy, Aritra Hazra, Chester Rebeiro

SENSE: Sketching Framework for Big Data Acceleration on Low Power Embedded Cores

Ever-growing IoT demands big data processing and cognitive computing on mobile and battery operated devices. However, big data processing on low power embedded cores is challenging due to their limited communication bandwidth and on-chip storage. Additionally, IoT and cloud-based computing demand low overhead security kernel to avoid data breaches. In this chapter, we present, “SENSE”, Sketching and Encryption on Scalable heterogeneous Engine for data reduction and encryption. SENSE is a heterogeneous framework which consists of three important kernels: 1. sketching module for data reduction, 2. an accelerator for efficient sketch recovery using scalable and parallel reconstruction architecture and 3. a host processor to perform post processing. SENSE framework can reduce data up to 67% with 3.81 dB signal-to-reconstruction error rate (SRER). One of the critical challenges in big data processing on embedded hardware platforms is to reconstruct the sketched data in real-time with stringent constraints on error bounds and hardware resources. We explore Orthogonal Matching Pursuit (OMP) algorithm for sketch data recovery. OMP is a greedy algorithm with high computational complexity which has emerged as an important tool for signal recovery, dictionary learning and sparse data classification. We use a domain specific many-core hardware named Power Efficient Nano Cluster (PENC) designed by EEHPC lab at University of Maryland, Baltimore County. To demonstrate efficiency of SENSE framework, we integrate it with Hadoop MapReduce platform for face detection application. The full hardware integration consists of tiny ARM cores which perform task scheduling and application processing, while PENC acts as an accelerator for sketch reconstruction. We show performance of SENSE framework on face identification application.
Amey Kulkarni, Tinoosh Mohsenin
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