6. Security Assessment of High-Level Synthesis

Securing intellectual property (IP) blocks have become a huge concern for the designers due to increasing attacks at different stages of the design. This wide array of attacks from IP piracy, counterfeiting, reverse engineering to overproduction has prompted designers to look into protection mechanisms to limit unauthorized access to the actual design. Logic locking/obfuscation is such a technique that protects designs from unauthorized usages by embedding locking keys into the design that are unknown to adversaries. However, the majority of the proposed locking techniques work at the gate-level of the design, and it has been shown that the correct keys can be successfully retrieved through various adversarial attacks such as SAT attacks, removal attacks, and reverse engineering. In this chapter, we propose a locking technique at a higher level of abstraction and show that using high-level synthesis, this technique is far more resilient towards different attacks and provides better control in terms of performance parameters to the designer compared to other techniques. The key element of this technique is locking the design at higher levels of abstractions (i.e., C/C++) when the designers have a better understanding of the design’s critical functions/information. In the next step, a high-level synthesis (HLS) tool is used to automatically generate locked RTL modules from an untimed C/C++ description. The proposed framework is dependent on HLS. As a result, design security also depends on a secure HLS process. For this purpose, we also provide a detailed security assessment on the HLS process and show potential vulnerabilities during its translation. We also present some verification approaches to address these vulnerabilities to secure the design and provide a robust framework for IP protection.