Self-Timed IC Design with PPL’s

PPL’s [8] are a cellular IC design tool derived from PLA [9, 2] and SLA [6, 7] ideas. They allow IC designs to be created by placing logical symbols on a grid. Modules thus created may be interconnected by placing additional cells on the grid. A design may be checked with a simulator [5] which reads the file created in the process of laying out the design. When the designer is satisfied with a design he may finish the process of creating a die by placing cells from the PPL pad cell set on a larger grid around his design, and connecting power, ground and the input and output signals from the pads to the power, ground and 10 points on his design with metal and/or poly wires. The wires also lay out on a grid that assures proper spacing between them. The cell symbols are then automatically replaced by the poly, metal and diffusion layout that realizes them and the resulting composite is fractured and dumped to tape in the format for the intended pattern generator.