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2019 | OriginalPaper | Buchkapitel

2. Sensing of Resistive RAM

verfasst von : Qing Yang, Bonan Yan, Hai Li

Erschienen in: Sensing of Non-Volatile Memory Demystified

Verlag: Springer International Publishing

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Abstract

Resistive random-access memory (ReRAM) is a promising non-volatile memory with the configurability of resistance programmed by pulse voltage or current. ReRAM can be used for memory and computation. In this chapter, we will start with these applications and design components for ReRAM. As the sensing schemes dominate the performance, the ReRAM sensing designs in storage and processing-in-memory (PIM) applications will be explained in detail.

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Literatur
1.
Zurück zum Zitat Song L, Qian X, Li H, Chen Y (2017) PipeLayer: a pipelined ReRAM-based accelerator for deep learning. In: High performance computer architecture (HPCA), 2017 IEEE International Symposium on, pp 541–552. IEEE Song L, Qian X, Li H, Chen Y (2017) PipeLayer: a pipelined ReRAM-based accelerator for deep learning. In: High performance computer architecture (HPCA), 2017 IEEE International Symposium on, pp 541–552. IEEE
2.
Zurück zum Zitat Shafiee A, Nag A, Muralimanohar N, Balasubramonian R, Strachan JP, Hu M, Williams RS, Srikumar V (2016) ISAAC: a convolutional neural network accelerator with in-situ analog arithmetic in crossbars. In: Proceedings of the 43rd international symposium on computer architecture, pp 14–26. IEEE Press Shafiee A, Nag A, Muralimanohar N, Balasubramonian R, Strachan JP, Hu M, Williams RS, Srikumar V (2016) ISAAC: a convolutional neural network accelerator with in-situ analog arithmetic in crossbars. In: Proceedings of the 43rd international symposium on computer architecture, pp 14–26. IEEE Press
3.
Zurück zum Zitat Chi P, Li S, Xu C, Zhang T, Zhao J, Liu Y, Wang Y, Xie Y (2016) Prime: a novel processing-in-memory architecture for neural network computation in ReRAM-based main memory. In: Proceedings of the 43rd international symposium on computer architecture, pp 27–39. IEEE Press Chi P, Li S, Xu C, Zhang T, Zhao J, Liu Y, Wang Y, Xie Y (2016) Prime: a novel processing-in-memory architecture for neural network computation in ReRAM-based main memory. In: Proceedings of the 43rd international symposium on computer architecture, pp 27–39. IEEE Press
4.
5.
Zurück zum Zitat Liu C, Yan B, Yang C, Song L, Li Z, Liu B, Chen Y, Li H, Wu Q, Jiang H (2015) A spiking neuromorphic design with resistive crossbar. In: Design automation conference (DAC), 2015 52nd ACM/EDAC/IEEE, pp 1–6. IEEE Liu C, Yan B, Yang C, Song L, Li Z, Liu B, Chen Y, Li H, Wu Q, Jiang H (2015) A spiking neuromorphic design with resistive crossbar. In: Design automation conference (DAC), 2015 52nd ACM/EDAC/IEEE, pp 1–6. IEEE
6.
Zurück zum Zitat Jiang H, Zhu W, Luo F, Bai K, Liu C, Zhang X, Joshua Yang J, Xia Q, Chen Y, Wu Q (2016) Cyclical sensing integrate-and-fire circuit for memristor array based neuromorphic computing. In: circuits and systems (ISCAS), 2016 IEEE international symposium on, pp 930–933. IEEE Jiang H, Zhu W, Luo F, Bai K, Liu C, Zhang X, Joshua Yang J, Xia Q, Chen Y, Wu Q (2016) Cyclical sensing integrate-and-fire circuit for memristor array based neuromorphic computing. In: circuits and systems (ISCAS), 2016 IEEE international symposium on, pp 930–933. IEEE
7.
Zurück zum Zitat Chua L (1971) Memristor-the missing circuit element. IEEE Trans Circuit Theory 18(5):507–519CrossRef Chua L (1971) Memristor-the missing circuit element. IEEE Trans Circuit Theory 18(5):507–519CrossRef
8.
Zurück zum Zitat Strukov DB, Snider GS, Stewart DR, Williams RS (2008) The missing memristor found. Nature 453(7191):80–83 Strukov DB, Snider GS, Stewart DR, Williams RS (2008) The missing memristor found. Nature 453(7191):80–83
9.
Zurück zum Zitat Zhang L, Chen Z, Joshua Yang J, Wysocki B, McDonald N, Chen Y (2013) A compact modeling of TiO2-TiO2–x memristor. Appl Phys Lett 102(15):153503 Zhang L, Chen Z, Joshua Yang J, Wysocki B, McDonald N, Chen Y (2013) A compact modeling of TiO2-TiO2–x memristor. Appl Phys Lett 102(15):153503
10.
Zurück zum Zitat Chang M-F, Wu J-J, Chien T-F, Liu Y-C, Yang T-C, Shen W-C, King Y-C et al (2015) Low VDDmin swing-sample-and-couple sense amplifier and energy-efficient self-boost-write-termination scheme for embedded ReRAM macros against resistance and switch-time variations. IEEE J Solid-State Circuits 50(11):2786–2795CrossRef Chang M-F, Wu J-J, Chien T-F, Liu Y-C, Yang T-C, Shen W-C, King Y-C et al (2015) Low VDDmin swing-sample-and-couple sense amplifier and energy-efficient self-boost-write-termination scheme for embedded ReRAM macros against resistance and switch-time variations. IEEE J Solid-State Circuits 50(11):2786–2795CrossRef
11.
Zurück zum Zitat Lo C-P, Lin W-Z, Lin W-Y, Lin H-T, Yang T-H, Chiang Y-N, King Y-C et al (2017) Embedded 2 Mb ReRAM macro with 2.6 ns read access time using dynamic-trip-point-mismatch sampling current-mode sense amplifier for IoE applications. In: VLSI circuits, 2017 symposium on, pp C164–C165. IEEE Lo C-P, Lin W-Z, Lin W-Y, Lin H-T, Yang T-H, Chiang Y-N, King Y-C et al (2017) Embedded 2 Mb ReRAM macro with 2.6 ns read access time using dynamic-trip-point-mismatch sampling current-mode sense amplifier for IoE applications. In: VLSI circuits, 2017 symposium on, pp C164–C165. IEEE
12.
Zurück zum Zitat Chang Meng-Fan, Sheu Shyh-Shyuan, Lin Ku-Feng, Che-Wei Wu, Kuo Chia-Chen, Chiu Pi-Feng, Yang Yih-Shan et al (2013) A high-speed 7.2-ns read-write random access 4-Mb embedded resistive RAM (ReRAM) macro using process-variation-tolerant current-mode read schemes. IEEE J Solid-State Circuits 48(3):878–891CrossRef Chang Meng-Fan, Sheu Shyh-Shyuan, Lin Ku-Feng, Che-Wei Wu, Kuo Chia-Chen, Chiu Pi-Feng, Yang Yih-Shan et al (2013) A high-speed 7.2-ns read-write random access 4-Mb embedded resistive RAM (ReRAM) macro using process-variation-tolerant current-mode read schemes. IEEE J Solid-State Circuits 48(3):878–891CrossRef
13.
Zurück zum Zitat Sheu S-S, Chang M-F, Lin K-F, Wu C-W, Chen Y-S, Chiu P-F, Kuo C-C et al (2011) A 4 Mb embedded SLC resistive-RAM macro with 7.2 ns read-write random-access time and 160 ns MLC-access capability. In: Solid-state circuits conference digest of technical papers (ISSCC), 2011, IEEE International, pp 200–202. IEEE Sheu S-S, Chang M-F, Lin K-F, Wu C-W, Chen Y-S, Chiu P-F, Kuo C-C et al (2011) A 4 Mb embedded SLC resistive-RAM macro with 7.2 ns read-write random-access time and 160 ns MLC-access capability. In: Solid-state circuits conference digest of technical papers (ISSCC), 2011, IEEE International, pp 200–202. IEEE
14.
Zurück zum Zitat Han X, Jia Q, Sun H, Wang L, Wu H, Cai Y, Zhang F et al (2017) A 0.13 μm 64 Mb HfO x ReRAM using configurable ramped voltage write and low read-disturb sensing techniques for reliability improvement. In: Custom integrated circuits conference (CICC), 2017 IEEE, pp 1–4. IEEE Han X, Jia Q, Sun H, Wang L, Wu H, Cai Y, Zhang F et al (2017) A 0.13 μm 64 Mb HfO x ReRAM using configurable ramped voltage write and low read-disturb sensing techniques for reliability improvement. In: Custom integrated circuits conference (CICC), 2017 IEEE, pp 1–4. IEEE
Metadaten
Titel
Sensing of Resistive RAM
verfasst von
Qing Yang
Bonan Yan
Hai Li
Copyright-Jahr
2019
DOI
https://doi.org/10.1007/978-3-319-97347-0_2

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