2007 | Buch

# Simulation of Semiconductor Processes and Devices 2007

## SISPAD 2007

herausgegeben von: Dr. Tibor Grasser, Dr. Siegfried Selberherr

Verlag: Springer Vienna

2007 | Buch

herausgegeben von: Dr. Tibor Grasser, Dr. Siegfried Selberherr

Verlag: Springer Vienna

The "Twelfth International Conference on Simulation of Semiconductor Processes and Devices" (SISPAD 2007) continues a long series of conferences and is held in September 2007 at the TU Wien, Vienna, Austria. The conference is the leading forum for Technology Computer-Aided Design (TCAD) held alternatingly in the United States, Japan, and Europe. The first SISPAD conference took place in Tokyo in 1996 as the successor to three preceding conferences NUPAD, VPAD, and SISDEP. With its longstanding history SISPAD provides a world-wide forum for the presenta tion and discussion of outstanding recent advances and developments in the field of numerical process and device simulation. Driven by the ongoing miniaturization in semiconductor fabrication technology, the variety of topics discussed at this meeting reflects the ever-growing complexity of the subject. Apart from the classic topics like process, device, and interconnect simulation, mesh generation, a broad spec trum of numerical issues, and compact modeling, new simulation approaches like atomistic and first-principles methods have emerged as important fields of research and are currently making their way into standard TCAD suites.

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The semiconductor industry has clearly moved into the era of nanoelectronics where the “the understanding and control of materials at the sub-100nm level” — the best established definition of nanotechnology [

1

] — is essential to maintaining Moore’s Law. However nanoelectronics, like many other applications for nanotechnology, requires more than making single devices in small areas. To be commercially relevant, structures must be manufactured in volume and/or over large areas. And perhaps most fundamentally they must be produced at ever lower costs to drive adoption of new applications, grow end markets and provide the source of investment in next generation technology. In many instances, the invention of an appropriate manufacturing method may be of equal importance to the underlying device concept — there is perhaps no better example of than that of the IC itself where both Kilby (first realization) and Noyce (manufacturable process) are recognized as its primary inventors. We will define these methods of realization as “nanomanufacturing technologies” — i.e. the materials, process and measurement tools and technologies that deliver the required scale, cost, reproducibility and reliability to manufacture successful nanotechnology-based products.

We have developed an atomistic model for dopant diffusion in SiGe structures and we have implemented it in the kinetic Monte Carlo process simulator DADOS. The model takes into account (i) composition and stress effects on the diffusivity of interstitials, vacancies and dopants, (ii) SiGe interdiffusion, (iii) dopant segregation and (iv) the modifications of band-gap and charge levels. The model has been tested for B and Sb providing a very good agreement with available experimental data.

Possible arrangements of As in bulk Si have been investigated using ab initio calculations to establish the most stable configurations depending on As concentration and charge state. Consistently with these results we developed a continuous model for As activation and diffusion in Si. The model was implemented in the Sentaurus Process Simulator and calibrated using a wide range of experimental results available in the literature. It was independently tested for spike and flash annealing experiments with excellent results.

We have carried out molecular dynamics simulations of monatomic B and octadecaborane cluster implantations into Si in order to make a comparative study and determine the advantages and drawbacks of each approach when used to fabricate shallow junctions. We have obtained and analyzed the doping profiles and the amount and morphology of the damage produced within the target. Our simulation results indicate that the use of octadecaborane clusters for the implantation process shows several advantages with respect to monatomic B beams, mainly related to the reduction of channeling and the lower amount of residual damage at the end of range.

The optimal device structures and channel orientation for nanoscale strained-Ge heterostructure p-MOSFETs, are discussed through detailed Band-to-band-tunneling (including band structure and quantum effects), Low-field Mobility (k.p and Boltzmann Transport), Full-Band Monte-Carlo, and 1-D Poisson -Schrödinger Simulations. The tradeoffs between drive current (ION), intrinsic delay (τ), band-to-band-tunneling (BTBT) leakage and short channel effects (SCE) have been systematically compared in high mobility strained-Ge Heterostructure FETs (H-FETs).

Self-consistent full-band Monte Carlo (with multi-subbands) device simulations were performed to clarify the mechanism of drain-current enhancements for uniaxially strained bulk Ge-pMOSFETs with different channel/surface orientations. Unlike any conventional mobility studies, our device simulation enables us to probe fundamental roles of source-injection and channel backscattering in the practical bulk-MOSFET device structures with optimized channel/surface selections.

We have developed a system consisting of a full-3D process simulator for stress calculation and k · p band calculation that takes into account the subband structure. Our simulations are in good agreement with the experimental data of strained Si-pMOSFETs of 65nm technology devices. This system is a powerful tool to optimize device structures with all stress components.

A continuum model of phosphorus diffusion with germanium and carbon coimplant has been proposed and calibrated based on secondary ion mass spectroscopy (SIMS) profiles aiming at ultra shallow junction (USJ) formation in advanced CMOS technologies. The phosphorus diffusion behaviors are well captured by our model under various implant and annealing conditions, representing a significant step towards advanced n-type USJ formation technique using phosphorus and carbon coimplant for aggressively scaled CMOS technologies.

We present a model for build-up of intrinsic stress during the deposition of thin metal films. The model assumes a three-phase stress generation mechanism which corresponds to three characteristic phases of microstructure evolution. The simulation results based on the model are successfully compared with experimental results for Poly-SiGe PECVD films. The impact of critical parameter variation on mechanical properties of thin film is discussed.

We use grain-focused models to study grain boundary (GB) migration (GBM) in polycrystalline Cu vias that interconnect MLM layers in 3D ICs. Curvature-driven GB velocities are calculated by PLENTE [

1

]–[

3

] using the local mean curvature of the GBs, as described in Ref. 2. We use Comsol Multiphysics [

4

] to calculate GB velocities due to thermally induced strain energy jumps across GBs [

5

]. The thermo-mechanical calculations needed for this are made using model structures that combine continuum models and grain-continuum (GC) models (see [

1

]–[

3

], [

5

]); we call these ‘hybrid’ grain-continuum (HGC) models. Curvature driven GB dominates in this work; however, there are uncertainties in the absolute stress values used and how the relative magnitudes of these phenomena will change as the structure evolves.

As the design rule is scaled down, the electrical isolation of metal lines becomes critical. In a high density flash memory with 37nm (pitch=74nm) technology, the threshold voltage shift of ∼0.3V is found to be caused by tungsten micro-bridge between adjacent bit-lines. Simulations and experimental data showed that tungsten re-sputtering is occurred during the deposition of HDP (High Density Plasma)-SiO

2

used as the filling dielectric between tungsten bit-lines. In this paper, the model for the tungsten re-sputtering is presented. The plasma simulations are performed to investigate the effects of process factors of HDP-SiO

2

deposition on the formation of micro-bridge using in-house tool, PIE simulator.

An efficient algorithm is proposed for fast synthesis of low complexity model-based inverse lithography technology (ILT) and phase shift masks (PSM) to improve the resolution and pattern fidelity in optical microlithography. The patterns on the mask are transformed into frequency space using 2D discrete cosine transformation (DCT). The solution space is thus changed to frequency space from real space. By cutting off high frequency components in DC spectrum, the dimension of the solution space is greatly reduced. Using a gradient-based algorithm, we solve the inverse problem in incoherent and partial coherent imaging systems with binary, 6%EPSM and APSM mask. Good fidelity images are achieved.

The deep reactive ion etching process (DRIE) [

1

] is a time multiplexed process where a fast chemical etching and a passivation processes are applied alternatively. It is very popular in surface micro-machined MEMS processing to obtain trench structures with high aspect ratios. The presence of a thin passivation layer makes it a very challenging process, especially for the three-dimensional simulation analysis. In this work we present a modeling approach for the simulation of DRIE processes. The model has been implemented in the three dimensional process simulation framework

Victory-Process

. When varying the etching / deposition cycles’ time ratios, the DRIE process shows three different regimes. These regimes are as well represented by the developed model. The simulation results obtained are compared with the corresponding REM images of trench etching experiments.

This paper presents the results of a comparison among five Monte Carlo device simulators for nano-scale MOSFETs. These models are applied to the simulation of the I–V characteristics of a 25 nm gate-length MOSFET representative of the high-performance transistor of the 65 nm technology node. Appreciable differences between the simulators are obtained in terms of simulated I

ON

. These differences are mainly related to different treatments of the ionized impurity scattering (IIS) and pinpoint a limitation of the available models for screening effects at very large carrier concentrations.

A rigorous surface roughness scattering model for ultrathin-body SOI MOSFETs is presented, which extends Ando’s model for bulk MOSFETs. The matrix element of the scattering potential includes a generalized Prange-Nee term and all the Coulomb interaction terms. Using this model, we study the effects of the silicon body thickness, effective field, and dielectric constant of the insulator on the roughness-limited low-field electron mobility in ultrathin-body SOI MOSFETs.

We present a comparison between two-different approaches to including quantum effects in a Monte-Carlo simulator. The ability of our original Pearson Effective Potential (PEP) correction to correctly account for electrostatic quantum effects has been demonstrated on double-gate nMOS capacitors with different film thicknesses. In this work, results obtained from semi-classical, PEP corrected and multi-subband Monte-Carlo approaches are reported for a double-gate nMOSFET with a channel length L

C

= 20nm and a silicon film thickness T

Si

= 8 nm at low and high drain voltages. For the first time, excellent agreements are obtained between quantum corrected and multi-subband Monte-Carlo methods on both electrical characteristics and microscopic quantities.

The Pauli principle, which limits the occupancy of a single state to one electron, is included in a deterministic solver for the Langevin-Boltzmann equation (LBE) based on a spherical harmonics expansion. The Newton-Raphson scheme for solving the nonlinear BE converges within a few steps and the increase in CPU time is less than a factor of ten. Even in the case of an extremely degenerate electron gas no numerical problems occur. The approach works well for transport and noise, and the Nyquist theorem is satisfied with high numerical precision at equilibrium. For electrons in bulk silicon a non-negligible impact of the Pauli principle is found only at very high electron densities.

Electron-phonon coupling is central to semiconductor transport simulation. It is often treated in the simple Fermi’s Golden Rule formulation, but even at modest fields, such as those commonly present in modern semiconductor devices, finite state lifetime effects become important. Such effects are treated formally by including self-energy in the scattering formulation [

1

,

2

]. In order to make the problem more tractable, especially for efficient Monte Carlo simulation, various simplifying assumptions are made. The most common form is to assume a Lorentzian distribution. This assumption is well justified by perturbation theory, and is simple to calculate and implement. In the limit of infinite state life-time, it collapses to the energy-conserving delta function of the Fermi’s Golden Rule. On the other hand, when non-zero broadening is present, energy is no longer conserved, and this has been noted in some cases to lead to accumulated broadening [

3

]. Such accumulation of energy can lead to non-physical results and push the electron energy distribution into the hot electron regime. Our goal is to explore the reasons for this accumulation of energy and propose remedies which can be implemented in standard simulation tools.

A simple technique that can be implemented in the Monte Carlo (MC) simulation of transport in a quantum well is reported. The main difference between the proposed technique and existing methods is the use of three dimension momentum (3Dk) particles in the simulation of a quantum region. The use of 3Dk particles within a quantum well structure facilitates the MC simulation of transport in nanoscale devices which contain both the classical and quantum regions.

In industrial environments, numerical simulation has become an indispensable tool for the development and optimization of especially front-end processes. In order to remain useful for future technology nodes, process simulation has to follow and partly even anticipate paradigm shifts of state-of-the-art processes and new materials for future nanoelectronic devices. Within this article, the author presents his personal view of unsolved and upcoming issues that have to be addressed and solved in future.

1/

f

noise in MOSFETs under large-signal excitation, which is important in CMOS analog and RF circuits, is modeled as a perturbation in the semiconductor equations employing the oxide-trapping model. The oxide-trapping model for a MOSFET in periodic large-signal operation shows that 1/

f

noise reduces more than the small-signal noise model predicts as the gate OFF voltage decreases further below the threshold voltage.

The intrinsic parameter fluctuations induced by random discrete dopants (RDD) in nano-scaled MOSFETs are studied by applying the quantum mechanical approach. The increase of effective oxide thickness (EOT) by the quantum mechanical corrections generally makes gate controllability worse. However, as far as ultra thin body (UTB) devices, the increase of EOT improves gate controllability by suppressing leakage current because it reduces electrical body thickness by the constraint of the physical body thickness.

A methodology for mesh generation with nodes placed on the atomic positions of the structure is presented. The meshing strategy is based on the use of patterns to decompose a unit cell of the target crystal into tetrahedra. The mesh generation procedure has been applied to crystalline Si and SiO

2

(α-quartz) as well as to their interface. The constructed meshes have been consequently randomly populated by dopants using Monte Carlo approach. The dopants are replacing silicon atom in nodes of the crystal. The ‘atomistic’ mesh populated with random discrete dopants has been used to simulate an ensemble of microscopically different double gate MOSFETs in order to demonstrate the functionality of the meshing methodology.

The influence of line edge and gate interface roughness on SOI-MOSFET performance is studied by simulation. Both types of roughness were implemented in the device simulator SIMBA through the Fourier synthesis approach and the simulations were performed with the drift diffusion and the quantum drift diffusion models. Scaled transistors showed more sensitivity to rough interfaces with shallow junctions.

Numerical study in conjunction with comprehensive bending experiments has demonstrated that (100)-Si has the optimum channel direction along <110> in terms of the device performance of strained 65nm-node nMOSFETs with Contact Etch Stop Layer (CESL), and that both the shear strain component and the quantum confinement effect play an important role in this superiority.

A novel stress enhancement effect based on the damascene gate process with embedded SiGe (eSiGe) S/D for pFET is analyzed in detail, using stress simulation and Ion measurement, for the first time. Removal of a dummy poly-Si gate eliminates the repulsive force from the gate with a resulting enhancement of lateral compressive stress from eSiGe S/D. The stress enhancement effect is proved by device fabrication and measurement. Furthermore, a new channel recess process is proposed and investigated. Channel recess further increases stress at the channel. This effect is also confirmed by measurement, resulting in 14% current enhancement.

Stressed etch stop liners (ESL) are a common way to increase device performance. Here we investigate the layout dependent channel stress for mono- and multi-layer deposition. By means of empirical pseudopotential method full band structures are calculated and based on full band Boltzmann equation mobilities are extracted. We present for the first time nonlinear mobility enhancement maps for two strain components, in channel

and

out-of-plane direction, showing that for typical ESL conditions both strain components are important for NFET and PFET.

Three-dimensional (3D) stress, process and device simulation is performed for nMOS-FETs with widths from 0.5 µm to 0.1 µm and gate lengths from 100 nm to 45 nm. Stress originates from a cap-liner with 2 GPa tensile stress. Drift-diffusion simulation with the linear piezoresistance model is employed considering either the position-dependence of stress or using a constant stress tensor obtained from averaging the stress in the source-side of the channel over a cuboid extending over the full device width.

Considering a space-dependent or a constant stress tensor turns out to yield almost the same linear and saturation current enhancements. This permits to use the constant stress obtained from 3D stress simulation for much faster 2D process and device simulation. In particular, also only one band structure is needed for Monte Carlo device simulation.

The two-step recessed SiGe Source/Drain (S/D) structure, which is one of the embedded SiGe S/D engineering techniques, is a leading candidate for advanced pMOSFETs from the viewpoint of good roll-off characteristics and high channel strain. In this paper, we reveal the merits of this technology for the application to the 32 nm technology node, including the methodology for suppressing the layout effect by TCAD analysis.

In this work, we investigate multiple FIN FinFET source/drain designs to reduce series resistance and source/drain-to-gate capacitance. The tradeoffs between the increased parasitic capacitance and reduced parasitic resistance are explored using 3D device simulations.

This paper reports a novel L-shaped Impact-ionization MOS (LI-MOS) transistor structure that achieves a subthreshold swing of well below 60 mV/decade at room temperature and operates at a low supply voltage. The device features an L-shaped or elevated Impact-ionization region (I-region) which displaces the hot carrier activity away from the gate dielectric region to improve hot carrier reliability and

V

T

stability problems. Device physics and design principles for the LI-MOS transistor are detailed through extensive two-dimensional device simulations. The LI-MOS transistor exhibits excellent scalability, making it suitable for augmenting the performance of standard CMOS transistors in future technology generations.

We developed a new prototype TCAD tool for wafer processing, particularly to predict BMD(bulk micro defects) distribution, metal gettering characteristics, stress/slip behaviors from the view points of industry such as device reliability and reproducibility. We present herein (i)system concepts and basic models of the tool, (ii)notable output results of BMD radius/profiles in terms of initial interstitial oxygen ([O

i

]) concentration and process sequences in conjunction with metal gettering and typical stress/slip behaviors. We also discuss thermal budget customization with emphasis on substrate stiffness and gettering efficiency for reliability and reproducibility improvements in scaled devices.

A compact model for a phase-change memory cell is presented and confirmed by measurement. The model reproduces the non-linear current-voltage behavior of both set and reset states. The temperature-dependent crystallization and amorphization of the phase-change layer are taken into account in order to express resistance changes between set and reset states. The heat of fusion is also taken into account in the calculation of the amorphization.

For SiO

2

pMOSFETs, the reaction diffusion model is well used to describe the NBTI degradation theoretically and the Ogawa model for hole trap generation is known exper imentally. However, there is not a good model of NBTI degradation for SiON devices. In this paper, we propose a nitrogen dependent hole trap generation model by extending these two models and present the NBTI degradation model for SiON pMOSFETs.

The confined states in ultra-thin Ge layers on oxide are investigated using three different state-of-the-art full-band methods. Contrary to the prediction of the simple effective mass approximation (EMA) and multiband-models that decoupled the Conduction Bands (CB) and the Valence Bands (VB), full-band calculations predicts much lower subband energy shifts due to quantum confinement.

We study the Si(100) inversion layer quantisation, capacitance and tunnelling characteristics in the case of a gradual band gap transition at the Si/SiO

2

interface. A linear band gap transition of 0.5 nm at the SiO

2

side results in nearly 20% redistribution of carriers from the 2-fold to the 4-fold degenerate valley, due to the greater wave-function penetration and sub-band level lowering for the 4-fold valley. The gate capacitance is enhanced by up to 12% for a 1.0 nm nominal oxide thickness, and the direct tunnelling current density increases by an order of magnitude.

In this work, we show full-band calculations of the tunneling properties of ZrO

2

and HfO

2

high-

κ

oxides. First, we have determined semiempirical

sp

3

s*d

tight-binding (TB) parameters which reproduce ab-initio band dispersions of the high-

κ

oxides; then we have calculated transmission coefficients and tunneling currents for Si/ZrO

2

/Si and Si/HfO

2

/Si MOS structures. Results show a very low gate leakage current in comparison to SiO

2

-based structures with the same equivalent oxide thickness. The complex band structures of ZrO

2

and HfO

2

have been calculated; based on them we develop an energy dependent effective tunneling mass model. It is shown that this model can be used to obtain effective mass tunneling currents close to full-band results.

We conduct a thorough investigation of the tunneling dynamics of oxide traps in a-SiO

2

, in particular of the E

δ

′

center, the E

γ

′

center, their hydrogenated counterparts, and the H atom. Based on these findings their behavior in the context of tunneling can be deduced. It is found that an E

γ

′

center can exchange electrons with the Si bulk. The E

δ

′

center shows two distinct behaviors induced by a spread in its tunneling levels. The H atom is not affected by the presence of an interface, whereas a H bridge may occur in every charge state.

The electrostatics of InSb double-gate MOSFETs is simulated using a self-consistent solver which calculates channel bandstructure and carrier population by tight-binding (TB) approach. The

Q-V

g

characteristic and the Quantum Confinement Stark Effect (QCSE) are evaluated. By comparing with the results from the

k · p

method and effective mass approach, we show that full-band approach based on TB becomes more desirable when the channel is scaled down to a low dimensional quantum well. As the consequence of narrow channel width it is observed that the density of states (DOS) near band edges is decreased.

The effect of point defects such as oxygen vacancy and carbon interstitial on both electronic and structural characteristics of hafnium dioxide was analyzed by a quantum chemical molecular dynamics method. When a carbon atom as the impurity is introduced in hafnium dioxide, carbon impurity states (donor and acceptor) are formed in the band gap of hafnium dioxide. The band gap calculated from the energy difference between the donor and acceptor decreases to 1.6 eV. We conclude therefore, it is very important to control the composition of HfO

2

films in order to assure the electronic performance and reliability of hafnium dioxide film.

Science and technology at the nanoscale size offer today fundamental challenges in the field of device modeling. In this paper we document the growing interest of academies, institutions, and industries and the present impact on the market, and discuss different design strategies that have been proposed and/or implemented, aimed at the practical realization of innovative nanodevices. Few main examples of ideas and devices, namely ion-channel nano-biosensors, biomimetic sensors, molecular devices, solid-state components for quantum computation, nanotube electronics, and non-volatile nanomemo-ries, are also revised.

High density of interface traps at the SiC-SiO

2

interface gives rise to lower mobilities and currents in SiC MOSFETs. Detailed investigations are performed to measure and characterize these interface traps using experimental and modeling methods [

1

–

3

]. Recent measurements of threshold voltage instabilities by fast I–V methods have shown that the SiC-SiO

2

interface not only contains fast interface traps, but also slower near-interface and oxide traps [

4

,

5

]. Steady state modeling and simulations cannot characterize the effects of each of these defects. We have hence developed a detailed time dependent modeling scheme for dynamic interface trap occupation, and incorporated it into our 2D transient device simulator. We use the transient modeling to separate out and individually characterize interface, near-interface and oxide traps in 4H-SiC MOS devices.

An electro-thermal, transient device simulation study of Silicon Carbide (SiC) power thyristors operating in a pulsed-power circuit at extremely high current density has been carried out within the drift-diffusion approximation and classical heat generation and transport theory using MEDICI* [

1

]. The convergence problems normally associated with Technology Computer-Aided Design (TCAD) simulations of SiC bipolar devices were overcome without artificially increasing the free carrier concentration by optical carrier generation, or by increasing the initial temperature (thermal carrier generation). The simulation results closely predict the actual operating conditions of the SiC thyristor in the pulsed-power circuit and are used to interpret the results of experimental failure limit studies [

2

]. It is shown that TCAD simulations can realistically predict the electrical and thermal properties of complex SiC bipolar semiconductor devices operating under fast transient, pulsed-power conditions.

Numerical device simulations show that slight extensions of the p-emitter thickness in 4H-SiC high voltage blocking bipolar pin diodes lead to a signi cant lowering of the forward voltage drop under high injection conditions at room temperature. The advantage of higher recombination currents in the enlarged p-region resulting from an enhanced excess carrier density overbalances the higher series resistance of the high-doped p-region. Both effects have their origin in the incomplete ionization of the acceptor dopants in the p-emitter. Hence, they become less signi cant at higher temperatures. A temperature dependent optimal p-emitter thickness is identi ed.

IGBT device destruction often occurs localized at the edge termination. Among various termination techniques, “variation of lateral doping” (VLD) is a promising candidate to increase the ruggedness of IGBT chips. We analyzed the time-dependent behavior of VLD edge termination during avalanche breakdown by numerical simulations demonstrating the advantage of this technique. Measurements on IGBT test devices with VLD edge termination are in agreement with the simulations.

Magnetotransport of holes in Si inversion layers of 1D MOS capacitors on arbitrarily oriented substrates is simulated. The

$$ 6 x 6 \vec k \cdot \vec p $$

Schrödinger equation is solved self-consistently with the confining electrostatic potential to calculate the 2D hole gas subband structure. The transport of holes within the channel is investigated by solving the stationary Boltzmann equation (BTE) for a small lateral driving electric field. The distribution function is either expressed as a polynomial of the magnetic field or expanded into harmonics of the polar angle within 2D

$$ \vec k $$

-space (Fourier expansion). The Hall factor and the second order magnetotransport coefficients are calculated. The approximation of the second order coefficient by the square of the channel mobility is shown to fail.

Role of scattering has been discussed as scattering still controls drain current of decananometer MOSFET’s, including the number of scattering events per unit length or gate length. Nevertheless, as scattering mechanisms have various angular dependences, in this paper, meanings of ‘number’ of scattering events are discussed and ‘effective’ scattering number is introduced to interpret quasi-ballistic transport. This concept is shown to be useful to understand the quasi ballistic transport and the role of various scattering mechanisms especially when back-scattering is not negligible.

We present a parameter extraction technique for higher-order transport models for a 2D electron gas in ultra thin body SOI MOSFETs. To describe 2D carrier transport we have developed a self consistent Schrödinger-Poisson Subband Monte Carlo simulator. The method takes into account quantization effects and a non equilibrium distribution function of the carrier gas, which allows an accurate description of the parameter behavior for high electric fields. Finally the results are compared with the transport parameters of 3D bulk electrons and the influence of the channel thickness on the mobility is investigated.

A robust algorithm to get the chemical potential of the particle reservoirs for the self consistent full 2D Schrödinger-Poisson solver is proposed. Using this algorithm we study the effect of junction depth on ballistic current. Simulation results show that shallow junctions come with much better on to off current ratio while it keeps the on-state transconductance at the same level as the deeper junction device.

We have extensively investigated transport properties of nanowire MOSFETs and single-electron/single-hole transistors by experiments and band calculations. Special focus has been placed on measurements and physics of the channel direction dependence and charge polarity dependence. We adopted a special device structure with a common n-type and p-type channel. We confirmed that a [110]-directed nanowire p-type FET has the smallest

V

th

fluctuations caused by the size variations. We also verified that a [100]-directed single-hole transistor is the best device for the single-charge transistor operations. Actually, we observed Coulomb blockade oscillations with the record high peak-to-valley-current ratio of 480 at room temperature in a [100] single-hole transistor.

As device sizes shrink towards the nanoscale, CMOS development investigates alternative structures and devices. Existing CMOS devices will evolve from planar to 3D non-planar devices at nanometer sizes. These devices will operate under strong confinement and strain, regimes where atomistic effects are important. This work investigates atomistic effects in the transport properties of nanowire devices by using a nearest-neighbor tight binding model (sp

3

s*d

5

-SO) for electronic structure calculation, coupled to a 2D Poisson solver for electrostatics. This approach will be deployed on nanoHUB.org as an enhancement of the existing Bandstructure Lab.

Source-to-drain tunneling is investigated for Si triple-gate nanowire transistors. The full-band quantum transport problem is solved in an atomistic basis using the nearestneighbor

sp

3

d

5

s*

tight-binding method. It is self-consistently coupled to the threedimensional calculation of the electrostatic potential in the device using the finite element method. This procedure is applied to the computation of

I

d

—

V

gs

transfer characteristics of transistors with different channel orientations such as [100], [110], [111], and [112] for gate lengths ranging from 4 nm to 13 nm. The subthreshold swing

S

is then extracted from the results to determine the scaling limit of nanowire transistors.

We report on Terahertz (THz) current oscillations in single-walled semiconducting zig-zag carbon nanotubes (CNTs) upon application of a step DC bias, as shown in Fig. 1. To investigate the electron transport on a tube with fundamental indices of

n

= 13 and

m

= 0, we developed a transient ensemble CNT Monte Carlo (MC) simulator. In the simulator, electron transport in time and space is resolved with the effects of charge distribution on the potential profile along the tube. The solution shows that electron-phonon resonances give rise to current, velocity and concentration oscillations upon application of a DC bias.

Atomistic hole transport simulation based on a nonequilibrium Green’s function method and a tight-binding approximation has been performed for two types of ultrathin double-gate silicon-on-insulator MOSFETs; (i) <100>-device on a {100} substrate where the current flows along the <100> direction and (ii) <110>-device on a {110} substrate where the current flow direction is the <110> direction. Simulation results show that the difference in crystalline orientation of the devices greatly affects ballistic hole current due to a strong confinement-induced mixing of heavy- and light-hole states.

We employ a three-dimensional (3D) particle-in-cell method coupling with finite-difference time domain scheme to simulate the electron emission in surface conduction electron-emitter displays (SEDs). This computational technique includes the space charge effects automatically. We thus explore the conducting mechanism, the emission efficiency, and the current density distribution on the anode plate with one field emission emitter.

We present a microscopic model of the photocurrent in quantum well solar cells (QWSC), based on the non-equilibrium Green’s function formalism (NEGF) for a multiband tight-binding Hamiltonian. The quantum kinetic equations are self-consistently coupled to Poisson’s equation. Relaxation and broadening mechanisms are considered by the inclusion of acoustic and optical electron-phonon interaction in a self-consistent Born approximation of the scattering self energies. Results are shown for the density of states, spectral response, current spectrum and IV-characteristics of single quantum well

pin

-structures.

A Monte Carlo method has been used to investigate the dynamics of a terahertz quantum cascade laser. The simulator follows the evolution of both electrons and photons and makes use of a special weighting procedure in order to cope with the huge variations in the number of photons. The laser turn-on time is found to be much longer than the time needed to establish the electron population inversion. Moreover, it presents an important statistical dispersion which reflects the “rare events” statistics of photon emissions during the initial stage. The response to a modulation of either optical losses or injected current has been investigated and the laser turn-on delay appears as the main factor that limits the response at high frequency.

We present the

Tiber

CAD multiscale device simulation software. The scope of the project is a full description of charge transport and optoelectronic properties of devices with embedded active regions of nanometer-scale. We show simulations of a GaN LED that requires modeling of strain, transport of electrons, holes and excitons and device heating.

We clarify the mechanism of single electron hopping and demonstrate single electron ocsillation via Si-dot, using a high-presice general-puprpuse device-simulator.

We simulate the spin transport properties in Schottky Barrier FET by ensemble Monte Carlo Method. Based on the three subbands approximations of 2DEG a more accurate model to calculate the spin precession frequency is adopted. With intra-subband and inter-subband scatterings fully considered, the three subbands approximation is compared with the single band approximation. We also examine the influence of the external electric field on the dephasing of the injected spin polarization. The simulation results can provide some guidance for the future design of SpinFET.

We present preliminary results of a discontinuous Galerkin scheme applied to deterministic computations of the transients for the Boltzmann-Poisson system describing electron transport in semiconductor devices. The collisional term models optical-phonon interactions which become dominant under strong energetic conditions corresponding to nanoscale active regions under applied bias. The proposed numerical technique, that is a finite element method which uses discontinuous piecewise polynomials as basis functions, is applied for investigating the carrier transport in bulk silicon and in a silicon

n

+

−

n

−

n

+

diode. Additionally, the obtained results are compared to those of a high order WENO scheme solver.

Formation of shock waves in two-dimensional electron channels by electrical signals is studied using analytical and numerical models based on hydrodynamic electron transport equations coupled with two-dimensional Poisson equation.

Two-dimensional transient simulations of AlGaN/GaN HEMTs are performed in which a deep donor and a deep acceptor are considered in a semi-insulating buffer layer. It is shown that lag phenomena and current slump could be reproduced. Particularly, it is shown that gate lag is correlated with relatively high source access resistance of AlGaN/GaN HEMTs, and that drain lag could be a major cause of current slump. The current slump is more pronounced when the deep-acceptor density in the buffer layer is higher and when an off-state drain voltage is higher, because trapping effects become more significant. It is concluded that an acceptor density in the buffer layer should be made low to minimize current slump, although current cutoff behavior may be degraded when the gate length is short.

An electrothermal Monte Carlo method is applied to study various GaN heterostructures designed to improve electron confinement in the channel of the structures. It is shown that the use of a p-type GaN buffer and the inclusion of a thin InGaN back-barrier below the channel in AlGaN/GaN HFETs improve the device pinch-off characteristics, but increase the influence of self-heating. Results show that the use of an AlGaN exclusion layer at the AlGaN/GaN interface increases both the device currents and temperatures.

For the needs of high electron mobility transistors (HEMTs) optimization a reliable software simulation tool is required. Due to the high electric field in the device channel a hydrodynamic approach is used to properly model the electron transport. We modify an existing hydrodynamic mobility model in order to achieve a better agreement with Monte Carlo (MC) simulation data and measured DC and AC characteristics of AlGaN/GaN HEMTs.

Two dimensional physical-based device simulations (Silvaco — “Atlas”) of breakdown voltage (

V

hr

) effect in AlGaN/GaN HEMTs (high electron mobility transistors) on silicon carbide (4H-SiC) device are preformed. The influence of novel single layer grating field plates (FPs), consisting of gate connected fingers and floating fingers, on

V

br

, obtained via the electric field distribution in the AlGaN layer is studied. We have found that the grating FPs reduce the electric field peaks and efficiently distribute the electrical filed along the AlGaN-layer and thus enhance device

V

br

, characteristics.

Physics-based numerical simulation of an AlGaN/GaN HEMT with additional A1N interlayer (IL) is carried out using both the drift-diffusion (DD) and hydrodynamic (HD) transport models. Assuming that free electrons are supplied by donor-like surface traps (STs) at the top of the AlGaN layer, we show that the A1N IL increases the 2D electron gas density and reduces the ST occupation. The HD model correctly describes ST recharging due to heating of the channel electrons and subsequent thermionic emission into the AlGaN layer. This recharging has a strong effect on channel transport, leading to the creation of a depletion domain, which expands towards the drain with increasing drain bias. The DD model does not include this effect and the depletion region remains unchanged as the drain bias increases.

Using embedded SRAM as a path, FinFET may enter manufacturing at 32nm. FinFET provides several advantages over the planar MOSFET structure—smaller size, larger current, smaller leakage, and less variation in threshold voltage. A compact model of multi-gate transistors will facilitate their adoption. BSIM-MG is a surface-potential based compact model of multi-gate MOSFETs fabricated on either SOI or bulk substrates. The effects of body doping are modeled. It can also model a double-gate transistor with independently biased front and back gates and asymmetric front and back gate work-functions and dielectric thicknesses.

The compact double-gate MOSFET model HiSIM-DG considering the volume inversion effects is developed solving the Poisson equation iteratively including bulk charge. The developed model reproduces the bias dependence of not only the surface but also the center potential of the silicon layer. The model proves accurate dependence of silicon layer thickness in comparison to the 2 dimensional device simulation results. It is observed that the volume inversion effect prevents devices from performance degradation for a reduction of device sizes.

In this paper, we will present the basic structure and the parameter extraction procedure for a compact model of a NAND Flash memory string working in Spicelike circuit simulators. To the author knowledge, this is the first Spice-like model of a NAND Flash memory string. This model is modular and simple to be implemented. It will allow accurately reproducing both DC and transient behavior of NAND Flash memories without increasing computational effort, thus becoming an indispensable tool for designers to optimize circuits especially in multi-level applications.

The surface-potential-based compact model for quantum effects in planar and double-gate MOSFETs is developed. The surface-potentials at source and drain sides are calculated with the effective field approximation and the quantum charge epxression. The drain current is calculated with the drift-diffusion model and quantum correction of the lateral field. One set of equations is used for both planar and double-gate structures.

A reduction in the number of parameters involved in the statistical compact model parameter extraction is necessary for the development of scalable compact modelling strategy. The impact of size of parameter set on the quality of statistical compact modelling is investigated in detail by HSPICE simulation at both device and circuit levels. Principal component analysis (PCA) is employed on a two- parameter set to demonstrate the possibility to corporate it into scalable statistical compact modelling strategy.

In this work, we first extract Hydrodynamic (HD) parameters from a computationally intensive full-band Monte Carlo (MC) solution via the MOCA simulator. We are then able to achieve good fits between the calibrated HD and MC velocity profile of a near ballistic double gated FET (DGFET). Moreover, we demonstrate good fits using bulk-Si HD parameters between the I–V characteristics of HD simulation and the measured data of deeply scaled Silicon nanowire field effect transistors (SNWFETs).

The performance of carbon nanotube field-effect transistors is analyzed, using the non-equilibrium Green’s function formalism. The role of the inelastic electron-phonon interaction on the both on-current and gate delay time of these devices is studied. For the calculation of the gate delay time the quasi-static approximation is assumed. The results confirm experimental data of carbon nanotube transistors, where the on-current can be close to the ballistic limit, but the gate delay time can be far below that limit.

Metal/carbon nanotube Schottky contacts are studied using particle Monte Carlo Simulation. The developed model is based on the WKB approximation and on the Landauer formula. Results are in fairly good agreement with experimental data.

We present a derivation of exponential shape functions for the convection diffusion problem. The shape functions are defined for triangular elements and can be regarded as an extension of the one-dimensional Scharfetter-Gummel discretization scheme to two dimensions. The shape function varies exponentially in the direction of the element field vector and linearly in the direction orthogonal to the element drift velocity vector. A conservative discretization scheme is constructed by means of the box method. The resulting element matrix is not necessarily an M-matrix. A measure to stabilize the discretization is briefly outlined.

In order to investigate the technological potential ascribed to semiconductor nanowires, it is paramount to include quantum effects into the models used to simulate carrier trans-port as well as optical and excitonic features of various nanowire layouts.

In particular, one needs to determine the energy eigenvalues and eigenfunctions of the charge carriers in terms of material parameters and tunable parameters, such as the external voltages and the wire radius. As the latter may be running from a few nanometers up to a few tens of nanometers, the number of occupied subbands may substantially in-crease. Consequently, a flexible Poisson-Schrödinger solver needs to be invoked to minimize the computational burden, especially when it is to be integrated into another Simulation program.

Atomistic simulations of transport properties of an ultra-scaled Silicon nanowire (SiNW) field-effect transistor (FETs) in a Gate-All-Around configuration are reported. The calculations have been obtained using a semi-empirical tight-binding representation of the System Hamiltonian based on first-principles density functional theory (DFT). An efficient non-equilibrium Green’s functions (NEGF) scheme has been implemented in order to compute self-consistently the charge density and the electrostatic potential in the SiNW Channel.

An alytical expression for the dependence of the nonparabolicity parameter on shear stress is presented. At 3 GPa the nonparabolicity parameter is shown to increase by a factor of 1.7. Stress dependence of the nonparabolicity parameter is verified by comparing the density-of-states obtained analytically and from the empirical pseudopotential method, and good agreement is found. Increase in the nonparabolicity parameter increases the after-scattering density-of-states and hence the scattering rates, which results in a 25% suppression of the mobility enhancement due to effective mass decrease in a 3 nm thin body FET at 3 GPa [110] stress.

It is announced that the Maxwell equations can be solved on unstructured grids using finite integration methods. Numerical experiments show that next to the finite-volume method, a discretization technique can be defined based on ‘finite-surface’ integration.

This paper describes a numerical method for a time-dependent quantum drift-diffusion model with emphasis on adaptive time discretization. The adaptive time step algorithm is proposed by introducing the derivative of the free energy of the system. The algorithm is evaluated for carrier transport simulations in n

+

-n-n

+

structures. The new algorithm significantly reduces the total number of time step required to reach the stationary state.

Device simulation needs are growing more diverse and it is difficult for traditional simulators to satisfy them while maintaining usability, maintainability, speed, and robustness. The Modular Device Simulator (MDS) is a completely new simulator framework that addresses this problem by providing simulation building blocks within a dynamic, runtime-configurable framework driven by a scriptable input parser. This flexible framework allows MDS to be applied to a wide range of problems that traditionally would have been handled by many independent codes. MDS has been applied to the 45 nm node and beyond, including advanced applications such as Schrödinger/drift-diffusion and non-equilibrium Green’s function (NEGF).

In this work, we included Poole-Frenkel (P-F) detrapping mechanism to our simulator to calculate programming/erasing characteristics of charge trapping memory, and comprehensively analyze the impacts of temperature, trap depth and parameters of P-F model on program window and erasing speed. Our results reveal that Poole-Frenkel effect could accelerate the erasing operation, but it also could reduce the program window and cause the electric characteristics sensitive to temperature.

The small dimensions of the on-chip interconnect structures provide the interesting opportunity of using the optimized model of dominant magnetic field even at very high operating frequencies for inductance and resistance extraction. The parameters are obtained from the field energy calculated from the magnetic field distribution in the simulation domain. Vector and scalar shape functions are used for finite element equation system assembling. Series of simulations for an on-chip spiral inductor at frequencies between 1 MHz and 100 GHz are performed to extract the parameters and to visualize the field distributions in the simulation area.

We report on several ultrafast electron transport phenomena occurring in wurtzite InN which are considered as the physical mechanisms responsible for the THz electric field radiation. We apply the ensemble Monte Carlo (EMC) method to simulate the streaming transport caused by (a) optical phonon emission and (b) impact ionization. Under specific conditions, in both streaming regimes the electron drift velocity reveals the sub-picosecond oscillations which are an indication of “readiness” of the semiconductor system to radiate an electric field in the THz range. We also investigate the electric field emission from InN and InAs surfaces induced by femtosecond laser excitation.

SiGe employment is, for the first time, proposed to enhance band-to-band-tunneling-induced hot electron injection (BBHE) in a p-channel flash by the analysis made with two dimensional device simulator MEDICI. Simulation results show that more than 100 times enhancement in the programming speed can be achieved in a proposed p-channel flash with 40% Ge in the surface SiGe channel. In addition, a Si-cap layer and HfO

2

tunnel dielectric are also incorporated to improve the interface quality. Up to 1000 times enhancement in BBHE injection programming speed is achieved in the case of a p-channel flash memory with surface SiGe layer and HfO

2

tunnel dielectric.

This paper describes advances and remaining challenges in unstructured 3D meshing techniques for both process and device simulations and parallelization of the process simulator FLOOPS. The meshing is performed using a point cloud manager to create points and an unstructured tetrahedral mesher. Distributed parallel techniques are used to parallelize the sparse matrix assembly and solution for 3D process diffusion simulations.

In this paper, we numerically study the discrete-dopant-induced characteristic fluctuations in 16nm silicon-on-insulator (SOI) FinFETs. For devices under different temperature condition, discrete dopants are statistically generated and positioned into the three-dimensional channel region to examine associated carrier transportation characteristics, concurrently capturing “dopant concentration variation” and “dopant position fluctuation”. Electrical characteristics’ fluctuations are growing worse when the substrate temperature increases, the standard deviation of threshold voltage increases 1.75 times when substrate temperature increases from 300K to 400K for example. This “atomistic” device simulation technique is computationally cost-effective and provides us an insight into the problem of discrete-dopant-induced fluctuation and the relation between the fluctuation and thermal effect.

This paper describes the hot-carrier (HC) behaviour of a high-voltage 0.35 µm n-channel lateral DMOS transistor (LDMOSFET). Self-heating effects during HC stress have to be taken into account for the HC stress analysis. Peak I

dlin

and I

dsat

degradations were observed at the stress bias V

G

= 0.8 V and V

G

= 2.5 ∼ 3.0 V, respectively. Together with TCAD simulations and measurements, one can clearly explain the HC effects occurring near the bird’s beak region and show their impact on the I

dlin

and I

dsat

degradations.

Upcoming organic devices like thin lm transistors or light emitting diodes require novel architectures and materials. In most cases, two main problems, namely poor carrier mobility in the bulk and elusive interface effects, are closely related due to contact dominated device behavior. A three-dimensional Kinetic Monte Carlo simulator has been developed mimicking simultaneously charge injection and propagation. This work deals with the representation of contact roughness by the means of the Gaussian Disorder Model.

A master equation model is developed for dark injection from a metallic electrode into a random hopping system, representing a conjugated polymer or a molecularly doped polymer. A master equation allows for the inclusion of the image force effect on the charge injection process and for a separate analysis of the forward hopping and back-flow components. This model yields the injection current as a function of electric field, temperature, energy barrier between metal and organic layer, and energetic width of the distribution of hopping sites. Good agreement with experimental data is found.

In this work, the RF performance of Si nanowire transistors (SNWTs) is computationally investigated, including RF figures of merit, impacts of parasitic effects and nanowire cross-sectional shape fluctuation caused by process variation. The simulated results show superior RF scalability of SNWTs and severe impacts of parasitic capacitance and process fluctuations. The influence of gradient doping profile in source/drain extension region of SNWTs on RF application is also studied.

In this work we present a study of the combined effects of the variation of process parameters and geometry in a 65 nm technology through consistent three-dimensional TCAD process and device simulations. Channel lengths and widths together with two critical process parameters obtained through a screening experiment are examined in a 3-level full-factorial design of experiments. The results show an increased impact of process variations for short and narrow structures.

A novel triple-gate MOSFET structure with polysilicon gate process is proposed using asymmetrical (n

+

p

+

) polysilicon gates. CMOS-compatible V

T

’s for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed by three-dimensional numerical simulations. Comparisons of device properties with the mid-gap metal gate are presented.

We present a statistical methodology for leakage power estimation, due to subthreshold and gate tunneling leakage, in the presence of process variations, for 65 nm CMOS. The circuit leakage power variations is analyzed by Monte Carlo (MC) simulations, by characterizing NAND gate library. A statistical “hybrid model” is proposed, to extend this methodology to a generic library. We demonstrate that hybrid model based statistical design results in up to 95% improvement in the prediction of worst to best corner leakage spread, with an error of less than 0.5%, with respect to worst case design.

As CMOS technology is advanced in recent years, the operation of SRAM becomes critical issue for further scaling. It is crucial for realizing the SRAM to keep static noise margin (SNM) and write margin (WM) large enough to get stability and overcome random dopant and process fluctuations. Also, suppression of leakage current is another key issue. The major sources of leakage current are the gate direct tunneling current, the sub-threshold leakage and the reverse biased band-to-band-tunneling junction leakage. To reduce total chip power, these leakage components must be suppressed.

In this paper, we have focused on the optimization of low power operation SRAM circuit for 32 nm node with TCAD optimizing the relationship among margin, leakage current and access time. To conduct the circuit design principle, we define the new quality factor and evaluate the 32nm SRAM performance with this defined formula.

Full 3D numerical process and device simulations have been performed in order to optimize device design of multigate FETs (MuGFETs) and the underlying fabrication processes. At first process simulation parameters have been calibrated to measurement data of pre-development process results. Based on this, device electrical performance has been assessed for different gate length, fin doping, implant conditions, fin height, fin width, gate oxide and box thickness by means of typical device parameters.

A comprehensive technique for the accurate extraction of the effective lateral doping abruptness and the spreading resistance components is applied to both Si (100) and Si (110) MOSFETs. The spreading resistance components under extension-to-gate overlap and spacer regions are successfully correlated to the lateral extension (EXT) doping abruptness by the relationship between on-resistance (R

on

) and overlap capacitance response (C

ov

). The lateral doping profile difference is extracted between (100) and (110) PMOS, which successfully explains higher external resistance in measured (110) PMOS.

To clarify the microscopic mechanism of Negative-Bias Temperature Instability (NBTI), which is one of serious reliability issues in CMOS technology, the transfer reaction of the positive fixed charge at the Si/SiO

2

interface accompanied by hydrogen migration was investigated using the ab initio molecular orbital method. Comparing the activation energies, we determined the most likely reaction path. We found that the reaction path can be stabilized more by migration of an electrically neutral H atom from a Si substrate to a positively charged O atom than by migration of a proton from a Si substrate to an electrically neutral O atom. The calculated Mulliken atomic charges and atomic spin densities also supported our conclusion.

One of the major challenges in deep submicron semiconductor era is to control the increase of variations due to decreasing in feature size. Currently, Design for Manufacturing (DFM) method enables to optimize layouts reducing the influence of process variations on circuit [

1

]. In this paper, we investigated the process margin analysis methods which are related to process defects of high aspect ratio (HAR) contact and short failures between lines. From this methodology, yield limiting process failures are identified and nano-scale defects in cells are virtually monitored without destructive method. This novel simulation methodology makes it possible to estimate the number of void defects of floating gate in Flash memory and predict Breakdown Voltage (BV) of the capacitor in DRAM. As a result, the defect level which is related yield has been decreased from 42% to 2.1% in 60nm Flash device and BV of capacitor has been virtually monitored in 80nm DRAM device.

We have developed a topography simulation method which combines advanced level set techniques for surface evolution with Monte Carlo flux calculation. The result is an algorithm with an overall complexity and storage requirement scaling like

O

(

N

log

N

) with surface disretization. The calculation of particle trajectories is highly optimized, since spatial partitioning is used to accelerate ray tracing. The method is demonstrated on Si etching in SF

6

/O

2

plasma.

Process induced stress is one of the key performance boosters to qualify advanced MOSFET technological node. 3D Finite Element simulation (FEM) is carried out to accurately model Contact Etch-Stop Layer (CESL) stress-related layout effects. Indeed, the corresponding stress field in transistors greatly depends on many parameters. Correlations with electrical measurements demonstrate results relevance. In addition to the effect of the transistor size, the environmental features of the MOSFET, such as the density of adjacent structures including dummy and Al-contact play a major role. As a result, differences in layout lead to considerably change the stress-induced transistor performance.

We proposed a simple model to simulate topography and composition of deposited films. Our model described topography and composition of deposited fluorocarbon films in C

5

F

8

/CO/O

2

/Ar plasma etching. Analysis of compositions facilitated making of the reactor and surface models, and our model could treat the gas flow and open width dependency of the SiO

2

etching. It was very useful in designing devices for easy manufacturing.

We present calculations for the transport properties of single molecules and carbon nanotubes (CNT) bridged between electrodes. Here we use two calculation methods. One is the recursion-transfer-matrix (RTM) method, which is a reliable tool to calculate accurate scattering waves in plane-wave expansions. Combined with the NEGF method and density-functional formalism, we perform calculations of transport properties through single molecules. The other is the time-dependent wave-packet approach. Based on the linear-response Kubo formula, we perform O(N) calculation for the transport of large systems. We apply the method for the CNT-FET device and find that the control of the contact to electrodes are crusial for the device performance.

In MEMS fabrication micro-mechanical components have to be partially released from a substrate. Selectively etching away sacrificial layers, such that a free standing structure remains, is a widely used technique for this purpose. Free standing structures allow MEMS devices to induce or to sense mechanical movements or vibrations.

During sacrificial etching lower etch rates than the blanket ones are observed. This reduction can be explained by additional factors like the transport of the etch medium and its etch reactants via the relatively narrow (in relation to the etch depth) already etched channel under the free standing structure.

Sacrificial etching is mainly controlled by process parameters like the etch agent concentration, chamber temperature, and pressure. Furthermore, local geometrical features and the nature of chemical reactions are responsible for different etch speeds at material boundaries and, therefore, they influence the propagation of the etch front. In order to analyze these effects we have developed a three-dimensional topography simulation tool and the required models for the etch rates.

This paper describes our ab initio method to evaluate the effective work function of a MOS metal gate on HfO

2

oxide which is different from the vacuum one because of the Fermi pinning. The computation relies on Density Functional Theory (DFT) and Many Body theory. Firstly a monoclinic cell is computed using DFT to obtain a band structure; this one is corrected using the GW approximation. Then a stack made of W + HfO

2

is computed and using Van de Walle and Martins method, the energy bands alignment along the stack is obtained. Finally HfO

2

energies in the stack are corrected according to our previous computation on the HfO

2

cell. This calculation brings an evaluation of the valence band offset at the W/HfO

2

interface and the effective work function of W on HfO

2

.

In this paper, we present our

ab-initio

study on energy configurations, minimum energy path (MEP), and migration energy for neutral indium diffusion in a uniaxial tensile strained {100} silicon layer. Our

ab-initio

calculation of the electronic structure allowed us to figure out transient atomistic configurations during the indium diffusion in strained silicon. We found that the lowest-energy structure (Ins - Si

i

Td

) consists of indium sitting on a substitutional site while stabilizing a silicon self-interstitial in a nearby tetrahedral position. Our

ab-initio

calculation implied that the next lowest energy structure is In

i

Td

, the interstitial indium at the tetrahedral position. We employed the nudged elastic band (NEB) method for estimating the MEP between the two structures. The NEB method allowed us to find that that diffusion pathway of neutral indium is kept unchanged in strained silicon while the migration energy of indium fluctuates in strained silicon.

A new deterministic approach to the electronic noise calculation based on the non-equilibrium Green’s function formalism with the electron-phonon scattering mechanisms is presented for nanoscale devices, and the diffusion noise phenomena at zero frequency are investigated. Our approach can handle the quantum effects naturally and it gives physical insight about the noise in nanoscale devices. As an application, silicon nanowire field effect transistor is considered and the numerical results show that the Johnson-Nyquist theorem is satisfied at equilibrium and the excess noise occurs in the presence of current transport.

A perturbation technique is developed for the analysis of random doping induced fluctuations (RDF) of small-signal equivalent circuit parameters in semiconductor devices. This technique is based on the computation of the doping sensitivity functions of parameters of interest by using the admittance matrix parameters and is applied to the study of RDF of equivalent circuit parameters in a 40-nm channel length MOSFET. The presented technique can be easily extended to the analysis of RDF in other semiconductor devices such as SOI, HEMT, etc.