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Journal of Electronic Testing
Erschienen in: Journal of Electronic Testing 2/2019

12.04.2019

Single Event Transient Propagation Probabilities Analysis for Nanometer CMOS Circuits

verfasst von: Shuo Cai, Weizheng Wang, Fei Yu, Binyong He

Erschienen in: Journal of Electronic Testing | Ausgabe 2/2019

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Abstract

As the feature size of CMOS transistors scales down, Single Event Transient (SET) has been an important consideration in designing modern radiation tolerant circuits because it may cause some failures in the circuit outputs. Many researches have been done in analyzing the impact of SET on nanometer CMOS circuits. However, it is difficult to consider numerous factors such as three fault masking effects, consecutive cycles, signal correlations and so on. In this paper, we have presented a new approach for analyzing the propagation probabilities of SET in logic circuits. All three fault masking effects have been considered uniformly and SET Propagation Probabilities Matrices (SPPMs) have been used to represent the SET Propagation Probabilities (SPPs) in current clock cycle. Based on the matrix union operations which we have defined, the SPPs in consecutive cycles can be calculated accurately and efficiently. Experimental results on ISCAS’89 benchmark circuits show that our approach is practicable.
Vorheriger Artikel Memory-Aware Design Space Exploration for Reliability Evaluation in Computing Systems
Nächster Artikel An Integrated on-Silicon Verification Method for FPGA Overlays

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Metadaten
Titel
Single Event Transient Propagation Probabilities Analysis for Nanometer CMOS Circuits
verfasst von
Shuo Cai
Weizheng Wang
Fei Yu
Binyong He
Publikationsdatum
12.04.2019
Verlag
Springer US
Erschienen in
Journal of Electronic Testing / Ausgabe 2/2019
Print ISSN: 0923-8174
Elektronische ISSN: 1573-0727
DOI
https://doi.org/10.1007/s10836-019-05791-2

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