As design features increase and sizes shrink and more transistors are squeezed into a system-on-a-chip (SoC) IC, the sheer number of on-chip devices far outstrips a design team’s ability to harness the full benefits of all the transistors. Furthermore, according to a Synopsys survey, one of the main reasons for bugs in first silicon designs is logic bugs. To address those needs the EDA community provides a large set of tools for the logic designer that includes simulation, formal verification and linting among others. To fully benefit from these tools, the logic design teams should use them as one environment rather than as separate tools. In this paper, we will demonstrate how this usage of linting, simulation and formal verification as one environment can provide a solution that is greater than the sum of its parts. Several groups at Intel from the Digital Enterprise Group (DEG) and the Mobility Group (MG) are reporting good results by using this flow.
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- Smart-Lint: Improving the Verification Flow
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