Source-End Layouts on ESD/LU Reliabilities in an HV 0.25 um 60 V nLDMOS

Latch-up (LU)/electrostatic discharge (ESD) protection inclinations of a high-voltage (HV) IC reliability are investigated in this chapter, where the test DUTs were fabricated by a 0.25 um 60 V BCD process. In order to effectively evaluate the LU and ESD reliabilities, the source-end layout in two manners were proposed and verified; all of them effectively improved the trigger voltage (V _t1) or the secondary breakdown current (I _t2) to enhance its ESD immunity. These two kinds of source-end layout are the P⁺ of discrete distributed type and P⁺ of bulk-contact numbers varied type, while these two different layout methods have their own advantages and disadvantages. It can be concluded that the ESD immunity level or the trigger voltage (V _t1) decreasing of a device can be improved by the source-end layout optimization in an HV process. Then, in this work, by using some layout techniques to improve the important reliability robustness, these strategies will be easily used and without added any additional process or mask in an HV process technology.