Ausgabe 1/2018
Inhalt (10 Artikel)
Vulnerability Analysis of Adder Architectures Considering Design and Synthesis Constraints
Mostafa Salehi, Ali Azarpeyvand, Armin Hajaboutalebi Aboutalebi
FFI4SoC: a Fine-Grained Fault Injection Framework for Assessing Reliability against Soft Error in SoC
Xiaozhi Du, Dongyang Luo, Kailun Shi, Chaohui He, Shuhuan Liu
NBTI and Power Reduction Using a Workload-Aware Supply Voltage Assignment Approach
Yang Yu, Jie Liang, Zhiming Yang, Xiyuan Peng
Adaptive Management Techniques for Optimized Burn-in of Safety-Critical SoC
Davide Appello, Paolo Bernardi, Conrad Bugeja, Riccardo Cantoro, Giorgio Pollaccia, Marco Restifo, Federico Venini
Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design
Toral Shah, Anzhela Matrosova, Masahiro Fujita, Virendra Singh
Exploring System Availability During Software-Based Self-Testing of Multi-core CPUs
Michael A. Skitsas, Chrysostomos A. Nicopoulos, Maria K. Michael
Automation of Test Program Synthesis for Processor Post-silicon Validation
Vasudevan Madampu Suryasarman, Santosh Biswas, Aryabartta Sahu