Journal of Electronic Testing

Editorial

Vishwani D. Agrawal

New Editors – 2019

2018 JETTA Reviewers

Test Technology Newsletter

Fault Tolerant Soft-Core Processor Architecture Based on Temporal Redundancy

Paulo R. C. Villa, Rodrigo Travessini, Roger C. Goerl, Fabian L. Vargas, Eduardo A. Bezerra

RTOS Solution for NoC-Based COTS MPSoC Usage in Mixed-Criticality Systems

Serhiy Avramenko, Massimo Violante

An Optimized NS2 Module for UHF Passive RFID Systems

Rahma Benfraj, Vincent Beroulle, Nicolas Fourty, Aref Meddeb

Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies

Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Gallière, Michel Renovell

Design of Two-Tone RF Generator for On-Chip IP3/IP2 Test

Shakeel Ahmad, Jerzy Dąbrowski

An Efficient Metric-Guided Gate Sizing Methodology for Guardband Reduction Under Process Variations and Aging Effects

Andres Gomez, Victor Champac

Metric-Driven Verification Methodology with Regression Management

Marek Cieplucha

A Layout-Based Rad-Hard DICE Flip-Flop Design

Haibin Wang, Xixi Dai, Younis Mohammed Younis Ibrahim, Hongwen Sun, Issam Nofal, Li Cai, Gang Guo, Zicai Shen, Li Chen

Impact of Negative Bias Temperature Instability on Gate-All-Around Flip-Flops

Shiva Taghipour, Rahebeh Niaraki Asli