Journal of Electronic Testing

Editorial

Vishwani D. Agrawal

Test Technology Newsletter

A Systematic Method for Arranging Diagnostic Tests in Linear Analog DC and AC Circuits

Michał Tadeusiewicz, Stanisław Hałgas

A Parallel Test Application Method towards Power Reduction

Ding Deng, Yang Guo, Zhentao Li

Power-Aware Optimization of SoC Test Schedules Using Voltage and Frequency Scaling

Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal

Reliability Model for Multiple-Error Protected Static Memories

Hadi Jahanirad

Link Testing: a Survey of Current Trends in Network on Chip

Babak Aghaei, Ahmad Khademzadeh, Midia Reshadi, Kambiz Badie

A Time-Optimized Scheme Towards Analysis of Channel-Shorts in on-Chip Networks

Biswajit Bhowmik, Jatindra Kumar Deka, Santosh Biswas

Total Ionizing Dose Effect and Single Event Burnout of VDMOS with Different Inter Layer Dielectric and Passivation

Jiongjiong Mo, Hua Chen, Liping Wang, Faxin Yu

A Bridged Contactless Measurement Technique for LC Tank Based Voltage-Controlled Oscillator

Zhe Liu, Xiao-Peng Yu, Teng-long Fan, Cheng Cao, Wen-Quan Sui

VI-Based Measurement System Focusing on Space Applications

L. E. Seixas, S. Finco, S. P. Gimenez