Journal of Electronic Testing

Editorial

Vishwani D. Agrawal

Test Technology Newsletter

Enhanced Low Complex Double Error Correction Coding with Crosstalk Avoidance for Reliable On-Chip Interconnection Link

M. Maheswari, G. Seetharaman

A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems

D. A. Tran, A. Virazel, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovich, H.–J. Wunderlich

An Accurate Combination of on-the-fly Interface Trap and Threshold Voltage Methods for NBTI Degradation Extraction

Cherifa Tahanout, Hakim Tahi, Boualem Djezzar, Abdelmadjid Benabdelmomene, Mohamed Goudjil, Becharia Nadji

Recovery Time and Fault Tolerance Improvement for Circuits mapped on SRAM-based FPGAs

Anees Ullah, Luca Sterpone

Analog Fault Diagnosis Using Conic Optimization and Ellipsoidal Classifiers

Mohamed A. El-Gamal, Abdel-Karim S. O. Hassan, Ahmad A. I. Ibrahim

The Use of Software Engineering Methods for Efficacious Test Program Creation: A Supportive Evidence Based Case Study

Stefan Vock, Omar Escalona, Colin Turner, Frank Owens

A Functional Approach for Testing the Reorder Buffer Memory

S. Di Carlo, M. Gaudesi, E. Sanchez, M. Sonza Reorda

Fault Detection of Linear Analog Integrated Circuit in Network

Deliang Li, Kaoli Huang, Changlong Wang