Stochastic Process Variation in Deep-Submicron CMOS

The CMOS technology has dominated the mainstream silicon IC industry in the last few decades. As CMOS integrated circuits are moving into unprecedented operating frequencies and accomplishing unprecedented integration levels (Fig. 1.1), potential problems associated with device scaling—the short-channel effects—are also looming large as technology strides into the deep-submicron regime. Besides that it is costly to add sophisticated process options to control these side effects, the compact device modeling of short-channel transistors has become a major challenge for device physicists.

One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key parameters affecting performance of integrated circuits [1]. Although scaling made controlling extrinsic variability more complex, nonetheless, the most profound reason for the future increase in parameter variability is that the technology is approaching the regime of fundamental randomness in the behavior of silicon structures where device operation must be described as a stochastic process. Electric noise due to the trapping and de-trapping of electrons in lattice defects may result in large current fluctuations, and those may be different for each device within a circuit.

In addition to device variability, which sets the limitations of circuit designs in terms of accuracy, linearity and timing, existence of electrical noise associated with fundamental processes in integrated-circuit devices represents an elementary limit on the performance of electronic circuits.

In the nanometer regime, the transistor scaling has been slowing down due to the challenges and hindrances of increasing variability, short-channel effects, power/thermal problems and the complexity of interconnect.

CMOS technologies move steadily towards finer geometries, which provide higher digital capacity, lower dynamic power consumption and smaller area resulting in integration of whole systems, or large parts of systems, on the same chip. However, due to technology scaling, integrated circuits are becoming more susceptible to variations in process parameters and noise effects like power supply noise, cross-talk reduced supply voltage and threshold voltage operation severely impacting the yield [1]. Since parameter variations depend on unforeseen operational conditions, chips may fail despite they pass standard test procedures. Similarly, the magnitude of thermal gradients and associated thermo-mechanical stress increase further as CMOS designs move into nanometer processes and multi-GHz frequencies [1]. Higher temperature increases the risk of damaging the devices and interconnects since major back-end and front-end reliability issues including electro-migration, time-dependent dielectric breakdown, and negative-bias temperature instability have strong dependence on temperature. As a consequence, continuous observation of process variation and thermal monitoring becomes necessity. Such observation is enhanced with dedicated monitors embedded within the functional cores [2]. In order to maximize the coverage, the process variation and thermal sensing devices are scattered across the entire chip to meet the control requirements. The monitors are networked by an underlying infrastructure, which provides the bias currents to the sensing devices, collects measurements, and performs analog to digital signal conversion. Therefore, the supporting infrastructure is an on-chip element at a global scale, growing in complexity with each emerging design.

One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key parameters affecting performance of integrated circuits. As the device gate length approaches the correlation length of the oxide-silicon interface, the intrinsic threshold voltage fluctuations induced by local oxide thickness variation will become significant. The trapping and de-trapping of electrons in lattice defects may result in large current fluctuations, and those may be different for each device within a circuit. At this scale, a single dopant atom may change device characteristics, leading to large variations from device to device. Finally, line-edge roughness, i.e., the random variation in the gate length along the width of the channel, will also contribute to the overall variability of gate length. Since placement of dopant atoms introduced into silicon crystal is random, the final number and location of atoms in the channel of each transistor is a random variable. As the threshold voltage of the transistor is determined by the number and placement of dopant atoms, it will exhibit a significant variation, which leads to variation in the transistors’ circuit-level properties, such as delay and power. In addition to device variability, which sets the limitations of circuit designs in terms of accuracy, linearity and timing, existence of electrical noise associated with fundamental processes in integrated-circuit devices represents an elementary limit on the performance of electronic circuits. Similarly, higher temperature increases the risk of damaging the devices and interconnects (since major back-end and front-end reliability issues including electromigration, time-dependent dielectric breakdown, and negative-bias temperature instability have strong dependence on temperature), even with advanced thermal management technologies.