Skip to main content
main-content

Über dieses Buch

Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Simulation tools were a research curiosity and in general were mistrusted by most designers and test engineers. In those days the programs were not user friendly, models were inadequate, and the algorithms were not very robust. The demand for simulation tools has been driven by the increasing complexity of integrated circuits and systems, and it has been aided by the rapid decrease in the cost of com­ puting that has occurred over the past several decades. Today a wide range of tools exist for analYSiS, deSign, and verification, and expert systems and synthesis tools are rapidly emerging. In this book only one aspect of the analysis and design process is examined. but it is a very important aspect that has received much attention over the years. It is the problem of accurate circuit and timing simulation.

Inhaltsverzeichnis

Frontmatter

Chapter 1. Introduction

Abstract
The design of an electronic circuit, traditionally, started with the designer who, with a mental picture, translated his or her ideas into the form of a circuit schematic. This step relied heavily on the human designer’s intuition, past experience, and knowledge to make reasonable approximations. This was followed by the “breadboarding” phase in which an actual prototype of the circuit was constructed from discrete components interconnected by external wires and was tested. The performance of the circuit, if not found satisfactory, was then improved by adjusting the circuit element values in a somewhat trial-and-error fashion.
Vasant B. Rao, David V. Overhauser, Timothy N. Trick, Ibrahim N. Hajj

Chapter 2. Overview of Simulation Techniques

Abstract
Simulation plays a major role in the process of designing an integrated electronic circuit. By using a simulator, the circuit designer can evaluate the performance of the design before going into the expensive and time-consuming manufacturing process. There are two basic approaches to simulating an integrated electronic circuit. The first, and more traditional, approach is to treat the circuit as a continuous dynamical system and obtain a set of nonlinear algebraic-differential equations with electrical variables such as voltage, current, and charge to describe its behavior. The objective of an analog simulator is to solve this set of equations, numerically, and obtain the detailed waveforms at various nodes in the circuit.
Vasant B. Rao, David V. Overhauser, Timothy N. Trick, Ibrahim N. Hajj

Chapter 3. MOS Network Partitioning and Ordering

Abstract
In this chapter an MOS network model that can be used to perform switch-level simulation is presented. The entire MOS network is first partitioned into several subnetworks, or blocks. The transistors within a block may be further partitioned into driver and pass transistors if so desired. The set of blocks is then partitioned into its strongly connected components (SCC). The SCCs in the network are then ordered for simulation.
Vasant B. Rao, David V. Overhauser, Timothy N. Trick, Ibrahim N. Hajj

Chapter 4. Switch-Level Timing Simulation

Abstract
Let Ω(N,M,Σ) be a partitioned MOS network in which the set of blocks Σ has been further partitioned into its strongly-connected components (SCC) Σ 1 2 ,…, Σ μ . Let ORD denote the ordering in which the SCCs have been scheduled for processing as described in Section 3.4. If an SCC is simple, i.e., it consists of exactly one block with no internal feedback, then it is simulated at the switch level by algorithms described in this chapter. By simulating or processing a block, we mean, obtaining the digital waveforms at the output(s) of the block given those at the inputs to the block over the entire time-interval of interest. In case the SCC is not simple, a special event-driven windowing technique, to be described in Chapter 5, is used to simulate the various blocks within the SCC. This special technique partitions the entire time-interval into several windows and uses the algorithms described in this chapter to simulate only the active blocks within each window.
Vasant B. Rao, David V. Overhauser, Timothy N. Trick, Ibrahim N. Hajj

Chapter 5. Simulating Strongly Connected Components

Abstract
In this chapter we discuss the use of a special windowing technique to simulate the blocks within a strongly connected component (SCC). The algorithm presented splits the entire time-interval of interest into various time-slots or windows such that all pairs of signal-transitions take place entirely within one of these windows. This is achieved by maintaining a sequential-list of intervals of transitions which is updated dynamically as the algorithm progresses. The algorithm is, in a sense, event-driven, since only those circuit-blocks that are active within a window are processed and the fanouts of the output nodes of these blocks are scheduled for processing in the future. We begin by reviewing two well-known and classical techniques, namely, the waveform relaxation method and the time-point relaxation method, that could be used to simulate the blocks within an SCC in the network. We will show that neither of these schemes is entirely suitable in our type of simulation; hence, there is a need for the event-driven windowing technique that we will present.
Vasant B. Rao, David V. Overhauser, Timothy N. Trick, Ibrahim N. Hajj

Chapter 6. Performance of Idsim2

Abstract
In this chapter we discuss the performance of IDSIM2, a switch-level timing simulator for MOS circuits using the algorithms described in the earlier chapters. IDSIM2 has been implemented in the C programming language and runs on a SUN 3/160 workstation using the UNIX operating system. The MOS network is described to IDSIM2 in a SPICE2 input format.
Vasant B. Rao, David V. Overhauser, Timothy N. Trick, Ibrahim N. Hajj

Backmatter

Weitere Informationen