Symmetrical and asymmetrical source configured multilevel inverter with reduced device count

Multilevel inverters (MLIs) have been widely accepted in several industrial applications. The advantages provided by MLI are achieved only through the use of several semiconductor switches and capacitors; consecutively increase the total system cost and complexity. To overcome the above limitations, this article develops a reduced device count hybrid MLI topology. The proposed MLI topology (PMLIT) can produce a 9-level voltage waveform with symmetrical sources and a 7-, 11-level output voltage waveform with asymmetrical sources using a single cell. In addition, PMLIT can be extended to produce any number of voltage levels by cascade connection of the cells with the built-in ability to produce both negative and positive voltage levels. Also, the voltage across the used capacitor is self-balanced without the use of any external components. The comparative investigation reveals the superior characteristics of the PMLIT in terms of the components and total blocking voltage over the newly and conventional topologies. Also, the calculated cost function shows that the PMLIT is more economical than the recently developed topologies. Finally, the viability of the PMLIT has been validated by conducting various tests on the simulation platform and also experimentally for 7, 9, 11 and 81 levels under diverse operating conditions.