Synthesis and simulation study of non-restoring cell architecture layout in perpendicular nano-magnetic logic

Nano-magnetic logic is one of the most competitive technologies of conventional metal oxide semiconductor-based designs. There is no current flow, and information is transferred via the magnetic force between the magnets. Because of this phenomenon, it has low power dissipation and operating in the megahertz frequency range. In this paper, perpendicular nano-magnetic logic (pNML) technology is used for designing a non-restoring divider circuit. First, a new three-dimensional layout of the Exclusive-OR (XOR) gate is proposed. This layout is extended to a new 1-bit full adder circuit, 1-bit non-restoring cell and a 4-bit non-restoring divider. According to our insight, the proposed non-restoring divider circuit in the pNML layout and use of the multilayer is the first time in the literature. The areas of the proposed layouts are 9.72 µm², 45.9 µm², 61.2 µm² and 3955.95 µm² for the XOR gate, full adder, non-restoring cell and non-restoring divider designs, respectively. The proposed FA consumes 44.25% less latency and 60% fewer layers than the existing state-of-the-art work. All the proposed layouts are implemented using the MagCAD tool.