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Erschienen in:
Introduction Kapitel lesen Erstes Kapitel lesen

2011 | OriginalPaper | Buchkapitel

2. System-Level and Architectural Trade-offs

verfasst von : Dr. Emanuele Lopelli, Dr. Johan van der Tang, Prof. Arthur van Roermund

Erschienen in: Architectures and Synthesizers for Ultra-low Power Fast Frequency-Hopping WSN Radios

Verlag: Springer Netherlands

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Abstract

This chapter focuses on high level design of ultra-low power wireless nodes. First, different system architectures are compared in order to assess advantages and drawbacks of each architecture from a power consumption point of view. Second, different modulation formats are compared and an optimal data-rate is chosen in order to minimize the average power consumption of the node. Finally, the most common transmitter and receiver architectures are reviewed.

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Vorheriges Kapitel Introduction
Nächstes Kapitel FHSS Systems: State-of-the-Art and Power Trade-offs
Fußnoten
1
For example if the hopping rate is three times the data-rate, then 2 errors will cause a bit error. For a hopping rate 5 times the data-rate, 3 errors are necessary to cause a bit error.
 
2
As it will be proven in Chap. 3 the serial acquisition technique is the most power efficient algorithm for PNC acquisition.
 
3
The remaining part of the synchronization consists in what is generally called tracking. During tracking, the phase difference between the two PNCs is reduced to virtually zero from a closed-loop system (like a PLL). This system also tracks any instantaneous variation of the phase of the transmitter PNC in order to assure a constantly aligned PN sequences between the transmitter and the receiver when the nodes are communicating with each other.
 
4
With the word “ideal” here it is supposed that the channel is AWGN.
 
5
The 2-FSK noise bandwidth can be approximated by the Carson rule as B noise=2(Δf+f m) where \({f_{\mathrm{m}}}=\frac{2}{{T_{\mathrm{s}}}}\) with \(\frac{1}{{T_{\mathrm {s}}}}\) the data rate and Δf the frequency deviation.
 
6
For a 2-FSK modulated signal it equals four times the data rate.
 
7
External components require in general matching to 50 Ω. This means that the stage preceding the external component must be able to drive a 50 Ω impedance. Such a low impedance level will cost a high current consumption.
 
8
Considering a required sensitivity level of −76.5 dBm at 2.4 GHz, then the signal at the output of an LNA with gain equal to 15 dB is generally smaller than 1 mV rms.
 
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E. Lopelli, J.D. van der Tang, A.H.M. van Roermund, A 1 mA ultra-low-power FHSS TX front-end utilizing direct modulation with digital pre-distortion. IEEE J. Solid-State Circuits 42, 2212–2223 (2007) CrossRef
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Metadaten
Titel
System-Level and Architectural Trade-offs
verfasst von
Dr. Emanuele Lopelli
Dr. Johan van der Tang
Prof. Arthur van Roermund
Copyright-Jahr
2011
Verlag
Springer Netherlands
Buch
Architectures and Synthesizers for Ultra-low Power Fast Frequency-Hopping WSN Radios

Print ISBN: 978-94-007-0182-3

Electronic ISBN: 978-94-007-0183-0

Copyright-Jahr: 2011

DOI
https://doi.org/10.1007/978-94-007-0183-0_2

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