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2016 | Buch

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SystemVerilog Assertions and Functional Coverage

Guide to Language, Methodology and Applications

verfasst von: Ashok B. Mehta

Verlag: Springer International Publishing

Enthalten in: Springer Professional "Wirtschaft+Technik" , Springer Professional "Technik"

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Über dieses Buch

This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and SystemVerilog Functional Coverage. Readers will benefit from the step-by-step approach to functional hardware verification using SystemVerilog Assertions and Functional Coverage, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question ‘have we functionally verified everything’. Written by a professional end-user of ASIC/SoC/CPU and FPGA design and Verification, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the modeling of complex checkers for functional verification, thereby drastically reducing their time to design and debug.

This updated second edition addresses the latest functional set released in IEEE-1800 (2012) LRM, including numerous additional operators and features. Additionally, many of the Concurrent Assertions/Operators explanations are enhanced, with the addition of more examples and figures.

· Covers in its entirety the latest IEEE-1800 2012 LRM syntax and semantics;

· Covers both SystemVerilog Assertions and SystemVerilog Functional Coverage language and methodologies;

· Provides practical examples of the what, how and why of Assertion Based Verification and Functional Coverage methodologies;

· Explains each concept in a step-by-step fashion and applies it to a practical real life example;

· Includes 6 practical LABs that enable readers to put in practice the concepts explained in the book.

Inhaltsverzeichnis

Frontmatter
Chapter 1. Introduction
Abstract
As is well known in the industry, the design complexity at 16 nm node and below is exploding. Small form factor requirements and conflicting demands of high performance and low power and small area result in ever so complex design architecture. Multi-core, multi-threading and Power, Performance and Area (PPA) demands exacerbate the design complexity and functional verification thereof.
Ashok B. Mehta
Chapter 2. SystemVerilog Assertions
Abstract
This chapter will start with definition of an assertion with simple examples, moving on to its advantages as applied to real life projects, who and what types of assertions need to be added for a given SoC project and the methodology components to successfully adopt assertions in your project.
Ashok B. Mehta
Chapter 3. Immediate Assertions
Abstract
This chapter will introduce the ‘Immediate’ assertions (immediate ‘assert’, ‘cover’, ‘assume’) starting with a definition and leading to detailed nuances of its semantics and syntax.
Ashok B. Mehta
Chapter 4. Concurrent Assertions—Basics (Sequence, Property, Assert)
Abstract
This chapter introduces basics of concurrent assertions namely ‘sequence’, ‘property’, ‘assert’, ‘cover’ and ‘assume’. It discusses fine grained nuances of Clocking of concurrent assertions and also implication operators, multi-threaded semantics, formal arguments, ‘bind’ing of assertions, severity levels, among other topics.
Ashok B. Mehta
Chapter 5. Sampled Value Functions $rose, $fell, $stable, $past
Abstract
This chapter introduces and provides applications for Sampled Value Functions $rose, $fell, $past, $stable. Note that there are also quite a few new sampled value functions introduced in 2009/2012 LRM (e.g. $changed, $rose_gclk, $sampled, etc.).
Ashok B. Mehta
Chapter 6. Operators
Abstract
This chapter is the big one! This chapter describes all the operators offered by the language (both for a ‘sequence’ and a ‘property’) including Clock Delay with and without range, Consecutive repetition with and without range, non-consecutive repetition with and without range, ‘throughout’, ‘within’, ‘and’, ‘or’, ‘intersect’, ‘first_match’, ‘if…else’, etc. Each of the operator description is immediately followed by examples and applications to solidify the concept.
Ashok B. Mehta
Chapter 7. System Functions and Tasks
Abstract
This chapter discusses in detail the System Functions and Tasks such as $onehot, $onehot0, $isunknown, $countones and Abort System Functions and Tasks such as $assertoff, $asserton, $assertkill. Note that the 2009/2012 LRM introduces quite a few new abort functions such as $assertpasson, $assertfailon, $assertvacuosoff, $assertcontrol, etc.
Ashok B. Mehta
Chapter 8. Multiple Clocks
Abstract
Introduction: This chapter describes multiply-clocked sequences and properties and clock flow semantics (how does clock flow from one clock domain to another). It also discusses all the operators that work on multiply-clocked properties such as ‘and’, ‘or’, ‘not’ etc. It also describes nuances of Legal and Illegal conditions of such properties and sequences.
Ashok B. Mehta
Chapter 9. Local Variables
Abstract
This chapter is entirely devoted to the dynamic Local Variables. Without the dynamic multi-threaded semantics and features of Local Variables, many of the assertions would be impossible to write. The chapter also lays out how operators such as ‘or’ and ‘and’ affect the workings of parallel threads forked off by Local Variables based assertions. There are plenty of examples and applications to help you weed through the semantics.
Ashok B. Mehta
Chapter 10. Recursive Property
Abstract
Recursive property simply states that a condition holds. The property calls itself with a correct non-overlapping implication operator and correct antecedent and consequent relation.
Ashok B. Mehta
Chapter 11. Detecting and Using Endpoint of a Sequence
Abstract
Introduction: This chapter describes the endpoint sequence detection methods such as .triggered (.ended in 2005 LRM) and .matched and their operation with overlapping and non-overlapping operators. Legal, illegal conditions and plenty of examples and applications are presented.
Ashok B. Mehta
Chapter 12. ‘expect’
Abstract
Introduction: This chapter describes the procedurally blocking statement ‘expect’ and its differences with the ‘assert’ statement.
Ashok B. Mehta
Chapter 13. ‘assume’ and Formal (Static Functional) Verification
Abstract
Introduction: This chapter describes ‘assume’ statement and its usage for ‘static formal’ (or ‘static functional’) and ‘constrained random’ methodologies.
Ashok B. Mehta
Chapter 14. Very Important Topics and Applications
Abstract
Introduction: This chapter addresses many important topics such as Asynchronous FIFO assertions, triggering concurrent assertions from procedural blocks, calling subroutines, sequences as formal arguments, as antecedent and as triggering condition in a sensitivity list.
Ashok B. Mehta
Chapter 15. Asynchronous Assertions!!!
Abstract
This chapter is solely devoted to Asynchronous Assertions, meaning the sampling edge of the assertion is not a synchronous clock rather an asynchronous edge. Special focus is on pitfalls of using an asynchronous assertion both as the sampling edge as well as an antecedent expression variable.
Ashok B. Mehta
Chapter 16. IEEE-1800-2009/2012 Features
Abstract
Introduction: This chapter describes all the new features of the 2009/2012 LRM. In that sense, it is a long chapter. It describes features such as ‘strong’ and ‘weak’ properties, abort system tasks, deferred immediate assertions, past and future global clock based sampling functions such as $rose_gclk, $fell_gclk, $rising_gclk, $falling_gclk, etc. It further covers ‘followed by’ property operators, ‘always’, ‘eventually’, ‘until’, ‘nexttime’, ‘case’, $inferred_clock and $inferred_disable. Finally, it goes into detail of the ‘let’ construct and ‘checkers’.
Ashok B. Mehta
Chapter 17. SystemVerilog Assertions LABs
Abstract
Introduction: This chapter through six labs with increasing difficulty to solidify the practical features of properties and sequences.
Ashok B. Mehta
Chapter 18. SystemVerilog Assertions—LAB Answers
Abstract
This chapter provides answers to all the LAB questions posed in previous chapter, namely, answers for the following LABs are presented.
Ashok B. Mehta
Chapter 19. Functional Coverage
Abstract
Ah, so you have done everything to check the design. But what have you done to check your testbench? How do you know that your testbench has indeed covered everything that needs to be covered? That’s where Functional Coverage comes into picture. But first let us make sure we understand difference between the good old Code Coverage and the new Functional Coverage methodology.
Ashok B. Mehta
Chapter 20. Functional Coverage—Language Features
Abstract
Introduction: This chapter covers the entire language “Functional Coverage”. We will cover the following features in the upcoming sections.
Ashok B. Mehta
Chapter 21. Performance Implications of Coverage Methodology
Abstract
Introduction: This chapter describes the methodology components of Functional Verification. What you should cover, when you should cover, performance implications and applications on how to write properties that combine the power of assertions with power of Functional Coverage.
Ashok B. Mehta
Chapter 22. Coverage Options
Abstract
Introduction: This chapter describes the Coverage Options offered by the language. Options for ‘covergroup’ type (both instance specific and instance specific per-syntactic level) are described. Practical project methodology based examples are provided that you can directly deploy in your project.
Ashok B. Mehta
Backmatter
Metadaten
Titel
SystemVerilog Assertions and Functional Coverage
verfasst von
Ashok B. Mehta
Copyright-Jahr
2016
Electronic ISBN
978-3-319-30539-4
Print ISBN
978-3-319-30538-7
DOI
https://doi.org/10.1007/978-3-319-30539-4

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