Zum Inhalt
Erweiterte Suche
Anmelden
Nach oben

Technology Mapping for LUT-Based FPGA

  • 2021
  • Buch
Verfasst von
Marcin Kubica
Adam Opara
Dariusz Kania
Buchreihe
Lecture Notes in Electrical Engineering
Verlag
Springer International Publishing
Enthalten in
Springer Professional "Wirtschaft+Technik"
Springer Professional "Technik"
insite
SUCHEN

Über dieses Buch

Dieses Buch behandelt ausgewählte Themen der automatisierten Logiksynthese, die FPGAs gewidmet sind. Die Autoren konzentrierten sich auf zwei Hauptprobleme: die Zersetzung der Multioutput-Funktionen und die Technologie-Kartierung. Zusätzlich wurde die Idee vorgestellt, in diesen Prozessen binäre Entscheidungsdiagramme (BDD) zu verwenden. Das Buch ist eine wissenschaftliche Monografie, die die jahrelangen Forschungsarbeiten der Autoren zusammenfasst. Infolgedessen enthält es eine große Anzahl experimenteller Ergebnisse, was es zu einer wertvollen Quelle für andere Forscher macht. Das Buch hat einen erheblichen didaktischen Wert. Seine Anordnung ermöglicht einen schrittweisen Übergang von grundlegenden Dingen (z.B. der Beschreibung logischer Funktionen) zu viel komplexeren Themen. Dieser Ansatz ermöglicht es weniger fortgeschrittenen Lesern, die beschriebenen Probleme besser zu verstehen. Darüber hinaus achteten die Autoren darauf, dass die im Buch beschriebenen Probleme durch praktische Beispiele untermauert wurden, dank derer der Leser selbst die komplexesten im Buch beschriebenen Probleme unabhängig analysieren kann.
Mit KI übersetzt

Inhaltsverzeichnis

Frontmatter
Chapter 1. Introduction
Abstract
The design process of digital systems requires the use of specialized computer-aided design (CAD) software. The diversity of digital circuit implementations and the domination of application-specific integrated circuits (ASICs) create many problems in the field of automatic synthesis. Describing the designed systems and converting description to a form implemented in hardware are challenging. These problems have contributed to the development of high-level forms of system description, which may include hardware description languages or even system description languages.
Marcin Kubica, Adam Opara, Dariusz Kania
Chapter 2. Methods for Representing Boolean Functions—Basic Definitions
Abstract
In the process of logic synthesis, the method of representing Boolean functions has great importance. The development of synthesis methods is inseparably connected with the search for new forms of description.
Marcin Kubica, Adam Opara, Dariusz Kania
Chapter 3. Binary Decision Diagrams
Abstract
An effective way to represent logic functions is the Binary Decision Diagram (BDD). The prototype of the BDD was the Binary Decision Programs (BDP), in which different nodes in a given path can be assigned the same variable.
Marcin Kubica, Adam Opara, Dariusz Kania
Chapter 4. Theoretical Basis of Decomposition
Abstract
Function decomposition is a key elements of logic synthesis. A substantial interest in decomposition has been observed since the introduction of FPGAs.
Marcin Kubica, Adam Opara, Dariusz Kania
Chapter 5. Decomposition of Functions Described Using BDD
Abstract
Representation of functions in the form of BDD forces the necessity of introducing appropriate algorithms of decomposition.
Marcin Kubica, Adam Opara, Dariusz Kania
Chapter 6. Ordering Variables in BDD Diagrams
Abstract
Ordering variables significantly affects the number of nodes in the BDD diagram. Many known methods of ordering limit the number of BDD nodes. Unfortunately, the minimum number of nodes in the diagram does not guarantee finding the best function decomposition.
Marcin Kubica, Adam Opara, Dariusz Kania
Chapter 7. Nondisjoint Decomposition
Abstract
In the process of decomposition, various models of disjoint decomposition, for which Xb ∩ Xf = Φ, are applied. The decomposition process can be optimized.
Marcin Kubica, Adam Opara, Dariusz Kania
Chapter 8. Decomposition of Multioutput Functions Described Using BDD
Abstract
In practice, multioutput functions instead of single functions are implemented. By using common dependencies for several functions, a realization that consumes a smaller number of logical resources of a programmable device than that if each function is separately treated can be achieved.
Marcin Kubica, Adam Opara, Dariusz Kania
Chapter 9. Partial Sharing of Logic Resources
Abstract
Decomposition of multioutput functions naturally offers the possibility of sharing some parts of the logic resources. The effective sharing of resources limits the number of logic blocks that are needed to implement the multioutput function.
Marcin Kubica, Adam Opara, Dariusz Kania
Chapter 10. Ability of the Configuration of Configurable Logic Blocks
Abstract
Configurable logic blocks (CLBs) are the main logic resources of an FPGA. In general, a CLB consists of a few logic cells.
Marcin Kubica, Adam Opara, Dariusz Kania
Chapter 11. Technology Mapping of Logic Functions in LUT Blocks
Abstract
The main goal of decomposition is an effective technology mapping of a function in an FPGA. A multioutput function is mapped to logic blocks, which in the simplest case can be simply LUTs. These blocks can carry out any logic function with a limited (usually small) number of variables. The proposed technology mapping is based on choosing cutting lines of BDD.
Marcin Kubica, Adam Opara, Dariusz Kania
Chapter 12. Technology Mapping of Logic Functions in Complex Logic Blocks
Abstract
In modern FPGA devices, the basic logic cell does not contain LUTs but does contain configuration logic blocks. These blocks contain several LUTs in their structure that are significantly linked to each other. The architecture of configurable logic blocks is focused on increasing the flexibility of these cells in terms of configuration possibilities.
Marcin Kubica, Adam Opara, Dariusz Kania
Chapter 13. Decomposition Methods of FSM Implementation
Abstract
In the group of digital circuits, we can distinguish between combinational circuits and sequential circuits. The mathematical model of the sequential system is an FSM. An FSM consists of a memory block and combination blocks that are responsible for controlling memory elements and setting output states.
Marcin Kubica, Adam Opara, Dariusz Kania
Chapter 14. Algorithms for Decomposition and Technological Mapping
Abstract
The methods described in this book lead to two synthesis strategies: dekBDD and MultiDec. The first one uses single cutting line for decomposition, and the second one multiple cuttings of BDD for decomposition. DekBDD and MultiDec strategies are appropriately described by Algorithm 1, and Algorithm 3.
Marcin Kubica, Adam Opara, Dariusz Kania
Chapter 15. Results of Experiments
Abstract
To prove the efficiency of the proposed algorithms, a series of experiments has been conducted. Popular benchmarks, which describe combinational circuits in the pla format, underwent experiments. Depending on the series of experiments, the results may vary slightly due to the settings of the synthesis tools.
Marcin Kubica, Adam Opara, Dariusz Kania
Chapter 16. Summary
Abstract
The motivation to write this book was to show the readers the issues related to logic synthesis for FPGAs. This book is a review of the research carried out by the authors in recent years. The authors presented the results of their work in a partial form in their scientific publications, to which they refer repeatedly in this book. The compilation of these studies in the form of a book allows a broader view of the problem of logic synthesis, and thus it allows more complete conclusions to be drawn from the obtained results, which is the main purpose of this chapter.
Marcin Kubica, Adam Opara, Dariusz Kania
Backmatter
Titel
Technology Mapping for LUT-Based FPGA
Verfasst von
Marcin Kubica
Adam Opara
Dariusz Kania
Copyright-Jahr
2021
Electronic ISBN
978-3-030-60488-2
Print ISBN
978-3-030-60487-5
DOI
https://doi.org/10.1007/978-3-030-60488-2

Informationen zur Barrierefreiheit für dieses Buch folgen in Kürze. Wir arbeiten daran, sie so schnell wie möglich verfügbar zu machen. Vielen Dank für Ihre Geduld.