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In the last few years CMOS technology has become increas­ ingly dominant for realizing Very Large Scale Integrated (VLSI) circuits. The popularity of this technology is due to its high den­ sity and low power requirement. The ability to realize very com­ plex circuits on a single chip has brought about a revolution in the world of electronics and computers. However, the rapid advance­ ments in this area pose many new problems in the area of testing. Testing has become a very time-consuming process. In order to ease the burden of testing, many schemes for designing the circuit for improved testability have been presented. These design for testability techniques have begun to catch the attention of chip manufacturers. The trend is towards placing increased emphasis on these techniques. Another byproduct of the increase in the complexity of chips is their higher susceptibility to faults. In order to take care of this problem, we need to build fault-tolerant systems. The area of fault-tolerant computing has steadily gained in importance. Today many universities offer courses in the areas of digital system testing and fault-tolerant computing. Due to the impor­ tance of CMOS technology, a significant portion of these courses may be devoted to CMOS testing. This book has been written as a reference text for such courses offered at the senior or graduate level. Familiarity with logic design and switching theory is assumed. The book should also prove to be useful to professionals working in the semiconductor industry.

Inhaltsverzeichnis

Frontmatter

Chapter 1. Introduction

Abstract
Very Large Scale Integration (VLSI) has enabled us to implement very complex circuits on a single chip. Complementary Metal Oxide Semiconductor (CMOS) technology has played a dominant role in allowing this to happen. The advantages of VLSI circuits are obvious. However, they do pose a problem. The problem is how do we test the VLSI chips to ensure that they function as they are supposed to. With chips containing a million or more transistors, testing has become a difficult and time-consuming job. Testing is becoming an increasing part of the time it takes from conception to marketing of a chip. This problem can only become more severe in the future.
Niraj K. Jha, Sandip Kundu

Chapter 2. Test Invalidation

Abstract
CMOS has become a very popular technology because of its low-power requirement and high density. However, an increase in the density of the chips also increases the complexity of testing. To further add to the woes of a testing engineer, new mechanisms have been identified through which a test derived for a CMOS circuit may be invalidated. In other words, a test may not be able to do its intended job. This is the topic of discussion in this chapter.
Niraj K. Jha, Sandip Kundu

Chapter 3. Test Generation for Dynamic CMOS Circuits

Abstract
The dynamic CMOS circuit techniques present us with an attractive alternative to static CMOS circuits. It is possible to achieve higher density and speed with these techniques at the expense of a slight increase in the power requirement. In this chapter we will explore the testability of combinational dynamic CMOS circuits.
Niraj K. Jha, Sandip Kundu

Chapter 4. Test Generation for Static CMOS Circuits

Abstract
In the previous chapter we discussed testing methods for combinational dynamic CMOS circuits. In this chapter we will concentrate on combinational static CMOS circuits. Test generation for a static CMOS circuit, as in the case of a dynamic CMOS circuit, can be done from either its gate-level model or its transistor-level description. We will discuss both the approaches.
Niraj K. Jha, Sandip Kundu

Chapter 5. Design for Robust Testability

Abstract
If a test set exists for a CMOS circuit which detects all the stuck-open faults in it in the presence of arbitrary circuit delays and timing skews, then the circuit is said to be robustly testable. We saw earlier in Chapter 2 that dynamic CMOS circuits, such as domino CMOS and cascode voltage switch logic circuits, are always robustly testable. However, this is not true for all static CMOS circuits. In this chapter, procedures for designing robustly testable static CMOS circuits will be discussed. Generally, the circuits are designed to be robustly testable with respect to single stuck-open faults. However, we will also discuss a method which guarantees robust testability with respect to multiple faults.
Niraj K. Jha, Sandip Kundu

Chapter 6. Self-Checking Circuits

Abstract
With the increasing complexity of digital systems, ensuring the reliability of computations has become an important issue. A number of methods have been presented for the design of fault-tolerant systems. The first step in such a design is to detect faults. We would like to detect the faults as soon as they occur in order to prevent data contamination. An important concept which allows us to detect transient as well as permanent faults is the self-checking concept. Since transient faults have begun to play a dominant role in this era of VLSI circuits, they can no longer be ignored. As the name implies, a self-checking circuit is capable of automatically exposing its own faults. Another advantage of self-checking circuits is that software diagnostic programs can be simplified or even eliminated. This concept is becoming more and more attractive because the area overhead on a chip required to implement this concept is going down with the increase in the complexity of the chips.
Niraj K. Jha, Sandip Kundu

Chapter 7. Conclusions

Abstract
In the previous chapters we have considered testing, design for testability and self-checking design of combinational static and dynamic CMOS circuits. Not much work has been done in the area of test generation for sequential CMOS circuits. Owing to the difficult and time-consuming nature of sequential circuit testing, usually only the stuck-at fault model is assumed even for CMOS circuits. In order to reduce the complexity of sequential circuit testing, design for testability techniques, such as scan techniques, are used. These techniques reduce the complexity of test generation to that of testing combinational circuits. For example, in the scan path technique [WILL73], the circuit has a normal mode of operation and a test mode. In the test mode the circuit flip-flops are interconnected to form a shift register (i.e. the scan path). It is easy to test such a scan path. The test patterns for the combinational part of the circuit are serially shifted in and the responses are serially shifted out through the flip-flops. A scan path technique called level-sensitive scan design (LSSD) was developed for latch-based systems [EICH77], and is extensively used in IBM. Some chip area penalty has to be paid to incorporate these design for testability features into the chip.
Niraj K. Jha, Sandip Kundu

Backmatter

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