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Über dieses Buch

This book highlights the complex issues, tasks and skills that must be mastered by an IP designer, in order to design an optimized and robust digital circuit to solve a problem. The techniques and methodologies described can serve as a bridge between specifications that are known to the designer and RTL code that is final outcome, reducing significantly the time it takes to convert initial ideas and concepts into right-first-time silicon. Coverage focuses on real problems rather than theoretical concepts, with an emphasis on design techniques across various aspects of chip-design.



Chapter 1. The World of Metastability

In a synchronous system, the data always has a fixed relationship with respect to the clock. When that relationship obeys the setup and hold requirements for the device, the output goes to a valid state within its specified propagation delay time. In synchronous systems, the input signals always meet the flip-flop’s timing requirements; therefore, metastability does not occur. However, in an asynchronous system, the relationship between data and clock is not fixed; therefore, occasional violations of setup and hold times can occur. When this happens, the output may go to an intermediate level between its two valid states and remain there for an indefinite amount of time before resolving itself or it may simply be delayed before making a normal transition.
Mohit Arora

Chapter 2. Clocks and Resets

The cost of designing ASICs is increasing every year. In addition to the non-recurring engineering (NRE) and mask costs, development costs are increasing due to ASIC design complexity. To overcome the risk of re-spins, high NRE costs, and to reduce time-to-market delays, it has become very important to design the first time working silicon.
Mohit Arora

Chapter 3. Handling Multiple Clocks

Designs involving single clocks are easy and simple to implement. But in actual practice, there are few practical designs that function on just one clock. This chapter deals with multiple clock designs, problems faced therein and solutions in order to get a robust design that works on multiple clocks.
Mohit Arora

Chapter 4. Clock Dividers

Typically most SoCs require a number of phase-related clocks to various components in the design. For the synchronous even division, the required clocks are generated by dividing the master clock by a power of 2. However, sometimes, it is desirable to divide a frequency by an odd or even fractional divisor. In these cases, no synchronous method exists without generating a higher frequency master clock.
Mohit Arora

Chapter 5. Low Power Design

In the good old days of IC design, before power became a significant design constraint, most chips were designed without concern for power consumption. This is not true anymore as requirements for lower power consumption continue to increase significantly as components become battery-powered, smaller and require more functionality.
Mohit Arora

Chapter 6. The Art of Pipelining

The ever-increasing demand for high speed ASICs is driving the requirement to increase circuit throughput in terms of calculations per clock cycle. The performance of an ASIC can be increased by pipelining but at an expense of increase in system latency and area.
Mohit Arora

Chapter 7. Handling Endianness

Consider the analogy of communicating the word “TEST” using four packets of one character each. The transmitting party sends data in following order: “T”(transmitted first) → “E” → “S” → “T”(transmitted last). Without sufficient information, the receiving party can capture and assemble the data in 16 different combinations. Similarly incase the word is communicated using two packets of two character each (“TE” and “ST”), receiving party can assemble data either as “TEST” or “STTE”, the latter being incorrect. For similar reasons, the difference in Endian-architecture in an System on Chip (or SoC) is an issue when software or data is shared between computer systems unless all computer systems are designed with same Endian-architecture. Incase software accesses all the data as 32-bit words; the issue of endianess is not relevant. However, if the software executes instructions that operate on data 8 or 16 bits at a time, and the data need to be mapped at specific memory addresses (such as with memory-mapped I/O), then the issue of endianess needs to be dealt with.
Mohit Arora

Chapter 8. Deboucing Techniques

When any two metal contacts in an electronic device to generate multiple signals as the contacts close or open is known as “Bouncing”. “Debouncing” is any kind of hardware device or software that ensures that only a single signal will be acted upon for a single opening or closing of a contact.
Mohit Arora

Chapter 9. Design Guidelines for EMC Performance

Electronic circuits tend to pick up radiated signals from other transmitters whether these sources are transmitting intentionally or not. These Electromagnetic Interference or EMI problems can prevent adjacent piece of equipment working alongside one another. As a result it is necessary to design for Electromagnetic Compliance (EMC) to avoid harmful electromagnetic interference in the system.
Mohit Arora


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