Three-Dimensional Integration of Semiconductors

The first chapter of the book introduces research and development history of three-dimensional (3D) integration technology. Concept of through-Si via (TSV) is old but the industrialization of 3D integration technology was leaded by 3D packaging technology first. 3D integration technology development using TSV have been conducted word wide since around 2000. This chapter describes the 3D technology development history from the beginning through 2012.

The second chapter describes the recent research and development history of three-dimensional (3D) integration technology. In this chapter we can see so many development activities in the word from 2013. It took 45 years from the beginning of TSV research and development for industry to begin high-volume manufacturing devices with this technology. Although some challenges related to reliability and cost remain.

Through-silicon via requires some unique process technologies. This chapter consists of four sub chapters. First sub chapter descibes deep silicon etching by “Bosch process.” The process adopts high aspect ratio and straight via. Some process paramaters are discussed.

Next sub chapter takes up steady-sate silicon etching process, also know as “non-Bosch process.” Physics and chemistry to realize fast and controlled deep silicon etching are discussed.

Third sub chapter deals with low temperature dielectric deposition. Unique liquid source chemical vapor deposition at low temperature and its properties are introduced.

Finally, electrodeposition of copper to fill high aspect ratio via is described. Electrochemical analysis, mathematical models of via filling, high-speed via filling and reduction of thermal expansion coefficient to avoid “copper pop-up” are discussed.

Wafer thinning/handling is one of the most important technology to enable TSV. More than ten years, many researchers and engineers have made great efforts to establish the process.

In this chapter four technical articles are involved on the issues.

First, uniformity of wafer thichness is discussed. Thickness uniformity of temporary bonded wafer with glue is great issue for TSV manufacturing. A new technology named “Auto-TTV (total thickness variation)” compensates glue thickness distribution as flat as possible.

Second article presents novel via exposure technique. Copper via exposure during thinning process have many risks such as Cu via smear, wafer burn or wafer contamination by Cu. In this article, in-situ grit cleaning and rate-controlled polishing are discussed.

Third article deals with wafer bonding material and debonding process. Laser assisted debonding is expected to enable stable wafer handling process. Chemically and thermally stable glue is introduced.

Fourth article describes bonder and debonder for temporary bonding process. Key process and performance for temporary bonding is well summarized.

This chapter focuses on bonding, wafer to wafer bonding, underfilling and die to die bonding with nonconductive film.

The first article introduces wafer to wafer bonding. Unlike temporary bonding in Chapter 4.3, permanent wafer bonding usually does not use glue and debonding process. Applications and known quality issues such as alignment accuracy, scaling, distortion, bonding strength and void are discussed.

Second article deals with underfill material. Two types of materials, capillary underfill and nonconductive paste. Void and warpage are the major issues of the material. Filler size, viscosity and mechanical properties are shown to be effective to improve these issues.

Final article describes film type underfill material, nonconductive film. It is used as pre applied die interconnecting adhesive in thermal compression bonding process. Design of material properties is presented. The issues of bonding process and the improved experimental results are also introduced.

Spectroscopic reflectometry is a nondestructive technique widely used to analyze the properties of materials as thin layer thicknesses are used in advanced packaging manufacturing. The technique is based on the propagation of waves into media. If a discontinuity is encountered, a part of its energy is reflected back to the injection point according to the well-known law of reflection. The reflected signal gives useful information about the system and, in particular, thicknesses of thin layers.

There are many challenges in 3D integration circuit (3D-IC) with through-Si via (TSV) and metal bumps to be solved before the volume manufacturing starts. The most serious concerns are implications of stress/strain and metal contamination on device reliabilities in 3D stacked chips. Influences of mechanical stress and strain are introduced in wafer thinning process for 3D integration. Cu TSVs and metal bumps introduce significant mechanical stress and strain into thinned Si wafer. Active region in the 3D-IC with a thinned Si wafer might be more easily affected by metal impurity contamination. Because an extrinsic gettering (EG) region for gettering metallic contaminants during IC process is eliminated by the wafer thinning process, Cu atoms diffuse from Cu TSV when the blocking property of the barrier layer in the TSV to Cu is not sufficient. These Cu atoms may diffuse into both dielectric and active region of Si substrate during the back-end process and cause the performance degradation and early breakdown of devices. In this chapter, the influences of mechanical stress/strain effects introduced by Si thinning and metal bump joining and Cu impurity contamination effect introduced from Cu TSV and grinded surface on device reliabilities in thinned IC chips are discussed. DRAM may be sensitively affected by various parameters introduced in a 3D integration process. The impacts of 3D integration processes on memory retention characteristics in thinned DRAM chip are introduced for reliable 3D DRAM.

Since the 3D integrated circuit (3D-IC) consists of several dies that are connected by the huge number of through-silicon vias (TSVs), the yield of a 3D-IC makes an impact on the chip cost. Therefore, development of testing technology for 3D-IC becomes essential for reducing the manufacturing cost of 3D-IC. In this chapter, we describe the testing technologies for 3D-IC. In Sect. 8.1, we marshal the issues that must be handled in the 3D-IC testing. From Sects. 8.2 to 8.4, we introduce the outlining of the proposed 3D-IC testing technologies in so far. From Sects. 8.5 to 8.7, we provide the 3D-IC testing technologies that are proposed by our research group in Japan.

Chapter 9 introduces the results of Japanese national research and development (R&D) initiative of 3D integration technology using through-silicon via (TSV) over the 5-year period from 2008 to 2012. Association of Super-Advanced Electronics Technologies (ASET) conducted the “Development on Functionally Innovative 3D-Integrated Circuit (Dream Chip) Technology Project,” and it was managed by the NEDO organization. The development subjects consisted of thermal management/chip-stacking technology, thin wafer technology, and 3D integration technology, ultrawide bus 3D-SiP, mixed signal (digital -analog) 3D, and heterogeneous 3D technology.