For high-performance custom VLSI chips, the layout of integrated circuits has often relied on the expertise of manual layout artists. The process of creating such manual layouts is time-consuming, tedious, and error-prone. As the size and complexity of VLSI circuits increase, the time required to create the layout, verify its correctness, and ensure that the timing specifications are met, increases drastically. At the same time, the available design cycle time has remained constant or even decreased. As a result, a strong need exists for intelligent tools to create correct layouts for various designs. Ideally, these tools should be able to generate layouts that are more compact, or at least as compact as those produced manually with a shorter turnaround time. In addition, the layout of circuits should meet all of the timing requirements specified by the designer.
Weitere Kapitel dieses Buchs durch Wischen aufrufen
- Timing-driven CMOS Layout Synthesis
Sachin S. Sapatnekar
- Springer US
- Chapter 6
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