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Erschienen in:
2011 | OriginalPaper | Buchkapitel
7. Timing Exceptions
verfasst von : Sanjay Churiwala, Sapan Garg
Erschienen in: Principles of VLSI RTL Design
Verlag: Springer New York
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Abstract
As seen in Chapter 3, most of the paths in a design need to meet certain timing requirements – specifically, that they should be captured at the destination at the immediately following active edge of the clock, and, should not interfere with the previous active edge of the clock on the destination. However, there are certain paths which need not follow the above requirements. In subsequent sections, you will see various situations and examples of why the timing on certain paths need not meet the single cycle requirement. These paths are called Timing exceptions
. There are three kinds of exceptions: